search for: r4

Hi all, Consider this ARM assembly code of a C function: 00008124 <foo>: 8124: push {r4, r6, r7, lr} 8126: add r7, sp, #8 8128: mov r4, r0 812a: ldrsb.w r0, [r2] 812e: cmp r0, #1 8130: itt lt 8132: movlt r0, #85 ; 0x55 8134:...

As Adrian said, we'd need to see the source of foo() to assess what the location-list for bar ought to be. Without actually going to look, I would guess that 'poplt' is considered a conditional move, therefore r4's contents are not guaranteed after it executes (i.e. it is a clobber). If one operand of 'poplt' is 'pc' then of course it is also a conditional indirect branch (which is probably but not necessarily a return). This combination might be worth handling differently for location...

https://bugs.freedesktop.org/show_bug.cgi?id=78161 Priority: medium Bug ID: 78161 Assignee: nouveau at lists.freedesktop.org Summary: [NV96] Artifacts in output of fragment program containing not unrolled loops with conditional break Severity: normal Classification: Unclassified OS: Linux (All)

...; + leaq tab_off(%rip), RBASE; \ >> + movl (RBASE,reg_i,4), reg_o; >> + >> +#define round_xor(tab_off, reg_i, reg_o) \ >> + leaq tab_off(%rip), RBASE; \ >> + xorl (RBASE,reg_i,4), reg_o; >> + >> #define round(TAB,OFFSET,r1,r2,r3,r4,r5,r6,r7,r8,ra,rb,rc,rd) \ >> movzbl r2 ## H,r5 ## E; \ >> movzbl r2 ## L,r6 ## E; \ >> - movl TAB+1024(,r5,4),r5 ## E;\ >> + round_mov(TAB+1024, r5, r5 ## E)\ >> movw r4 ## X,r2 ## X; \ >> - movl TAB(...

...; + leaq tab_off(%rip), RBASE; \ >> + movl (RBASE,reg_i,4), reg_o; >> + >> +#define round_xor(tab_off, reg_i, reg_o) \ >> + leaq tab_off(%rip), RBASE; \ >> + xorl (RBASE,reg_i,4), reg_o; >> + >> #define round(TAB,OFFSET,r1,r2,r3,r4,r5,r6,r7,r8,ra,rb,rc,rd) \ >> movzbl r2 ## H,r5 ## E; \ >> movzbl r2 ## L,r6 ## E; \ >> - movl TAB+1024(,r5,4),r5 ## E;\ >> + round_mov(TAB+1024, r5, r5 ## E)\ >> movw r4 ## X,r2 ## X; \ >> - movl TAB(...

> On Apr 27, 2018, at 7:48 AM, Son Tuan VU <sontuan.vu119 at gmail.com> wrote: > > Hi all, > > Consider this ARM assembly code of a C function: > > 00008124 <foo>: > 8124: push {r4, r6, r7, lr} > 8126: add r7, sp, #8 > 8128: mov r4, r0 > 812a: ldrsb.w r0, [r2] > 812e: cmp r0, #1 > 8130: itt lt > 8132: movlt r0,...

...const spx_coef_t *den, @ spx_word16_t *y, @ int N, @ int ord, @ spx_mem_t *mem, @ char *stack) .global iir_mem16 iir_mem16: stmdb sp!, { r4-r11, lr } ldr r5, [sp, #36] @ r0 = x, r1 = den, r2 = y, r3 = N ldr r4, [sp, #40] @ r4 = mem, r5 = ord cmp r5, #10 beq .order_10 cmp r5, #8 beq .order_8 ldmia sp!, { r4-r11, pc } @ Mon-supported order, return @ TODO:...

...if (status == 0xAA) { > *cpt = 3; > return 0xAA; > } else { > *cpt--; > return 0x55; > } > } > > return 0x55; > } > > @paul: Yes you are right, I have investigated the backend and it all > starts at *IfConversionPass*. *r4* is clobbered by *poplt*, and there's > no logic to handle conditional instruction in *DbgValueHistoryCalculator*, > thus the issue at the binary level. > > Son Tuan Vu > > On Fri, Apr 27, 2018 at 5:53 PM, <paul.robinson at sony.com> wrote: > >> As Adrian said,...

...status = 0xAA; } else { status = 0x55; } if (status == 0xAA) { *cpt = 3; return 0xAA; } else { *cpt--; return 0x55; } } return 0x55; } @paul: Yes you are right, I have investigated the backend and it all starts at *IfConversionPass*. *r4* is clobbered by *poplt*, and there's no logic to handle conditional instruction in *DbgValueHistoryCalculator*, thus the issue at the binary level. Son Tuan Vu On Fri, Apr 27, 2018 at 5:53 PM, <paul.robinson at sony.com> wrote: > As Adrian said, we'd need to see the source of f...

Hi all, I got a silly bug when compiling our project with the latest Clang. Here's the outputted assembly: > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4] > ldr r6, [r4, r6, lsl #2] > bx r6 For the code to execute correctly, either the _ldr_ should be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to come from the IfConvertion MachinePass. Here's is what it looks lik...

...; <ubyte> [#uses=1] switch ubyte %c8, label %loop_step [ ubyte 97, label %ret_true ubyte 98, label %ret_true ] Unfortunately, this generates really weird code on the LLVM 1.6 PowerPC backend: LBB_matches_1: ; regex6 lbz r4, 0(r3) LBB_matches_2: ; NodeBlock rlwinm r5, r4, 0, 24, 31 cmplwi cr0, r5, 98 blt cr0, LBB_matches_4 ; LeafBlock LBB_matches_3: ; LeafBlock1 rlwinm r4, r4, 0, 24, 31 cmpwi cr0, r4, 98 beq cr0, LBB_matches_8 ; ret_true b LBB_matches_...

...llo everyone, I am running into an obscure issue with ExpandPostRA. Does anyone recognizes the following: The pass replaces a real copy with a "transfer" instruction: ********** EXPANDING POST-RA PSEUDO INSTRS ********** ********** Function: main real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>, %D7<imp-def> replaced by: %R15<def> = TFR %R4, %D7<imp-def> The R4 is a subreg of D2 double register (basically R0:R1==D0; R4:R5==D2 etc.). After this copy D2 is dead, and is marked as such. Register allocator did not mark R4 as...

...tAdjustBeforeShift; +} + + +#define MtoSTR(s) #s + +#define Dump "call MMX_dump\n" + +#define BeginIDCT "#BeginIDCT\n"\ + \ + " movq " I(3)","r2"\n" \ + \ + " movq " C(3)","r6"\n" \ + " movq " r2","r4"\n" \ + " movq " J(5)","r7"\n" \ + " pmulhw " r6","r4"\n" \ + " movq " C(5)","r1"\n" \ + " pmulhw " r7","r6"\n" \ + " movq " r1","r5"\n"...

...swi r19, r1, 4 add r19, r1, r0 swi r0, r19, 8 addik r3, r0, 100 swi r3, r19, 20 swi r0, r19, 16 addik r3, r0, -2147483648 swi r3, r19, 24 swi r0, r19, 28 lwi r4, r19, 16 xor r3, r4, r3 lwi r4, r19, 20 or r3, r4, r3 addik r4, r0, 0 addik r5, r0, 1 swi r5, r19, 32 beqid r3, ($BB0_2) swi r4, r19, 36 lwi r3, r19, 36 swi...

On Fri, 7 Feb 2014, Timothy B. Terriberry wrote: > Martin Storsjo wrote: >> This is required in order to build using the built-in assembler >> in clang. > > These patches break the gcc build (with "Error: bad instruction"). Ah, right, sorry about that. > Documentation I've seen is contradictory on which order ({cond}{size} or > {size}{cond}) is correct.

...t is creating assembly like this one below. Block LBB1_9 was inserted to break the critical edge between blocks LBB1_3 and LBB1_8. But it changes the semantics of the original program, because, before, LBB1_8 was falling through LBB1_4, and now it is falling on LBB1_9. LBB1_3: ;no_exit lis r4, 21845 ori r4, r4, 21846 mulhw r4, r2, r4 addi r5, r2, -1 li r6, -1 srwi r6, r4, 31 add r4, r4, r6 mulli r4, r4, 3 li r6, 1 subf r2, r4, r2 cmpwi cr0, r2, 0 beq cr0, LBB1_9 ;no_exit LBB1_7: ;no_exit mr r...

...ode (disassembly of the actual machine code running on GPUs) of the version with widening looks significantly longer. Without widening (7 instructions): .L_1: /*0048*/ IMUL R2, R0, R0; /*0050*/ IADD R0, R0, 0x1; /*0058*/ ST.E [R4], R2; /*0060*/ ISETP.NE.AND P0, PT, R0, c[0x0][0x140], PT; /*0068*/ IADD R4.CC, R4, 0x4; /*0070*/ IADD.X R5, R5, RZ; /*0078*/ @P0 BRA `(.L_1); With widening (12 instructions): .L_1: /*0050*/...

...> if (status == 0xAA) { > *cpt = 3; > return 0xAA; > } else { > *cpt--; > return 0x55; > } > } > > return 0x55; > } > > @paul: Yes you are right, I have investigated the backend and it all starts at IfConversionPass. r4 is clobbered by poplt, and there's no logic to handle conditional instruction in DbgValueHistoryCalculator, thus the issue at the binary level. > > Son Tuan Vu > > On Fri, Apr 27, 2018 at 5:53 PM, <paul.robinson at sony.com <mailto:paul.robinson at sony.com>> wrote: &g...

...two instructions that set a loop-invariant mask beforehand), with some comments of mine: > > mov r12, #255 > orr r12, r12, #65280 > LBB1_1: > ldrsh r3, [r1] # loads a short that is sign-extended to 32 bits > mov r4, lr > cmp r3, #2048 > bge .LBB1_3 > and r4, r3, r12 # mask with 0xffff to convert to short again > lsl r4, r4, #16 # this lsl and the following > asr r5, r4, #16 # asr implement sign-extensio...

...714153 US C4 1.22 C 4 0.9 45 10-Jun-99 NA US C4 1.83 C 4 0.9 48 09-Aug-04 3.940454483 US C4 21.2 C 4 0.9 48 28-May-03 NA US C4 25.8 C 4 0.9 48 30-May-01 2.782824039 US C4 7.54 C 4 0.9 48 15-Aug-00 2.336292028 US C4 3.63 C 4 0.9 48 12-Aug-99 1.379220009 US C4 10.3 C 4 0.9 30 10-Aug-00 3.727704048 US R4 NA R 4 0.9 30 17-Aug-99 NA US R4 1.47 R 4 0.9 30 03-Jun-99 NA US R4 2.93 R 4 0.9 31 15-Aug-00 1.594104052 US R4 5.85 R 4 0.9 31 17-Aug-99 0.961643994 US R4 15.8 R 4 0.9 31 03-Jun-99 0.907288015 US R4 7.1 R 4 0.9 33 04-Jun-01 5.030724049 US R4 1.92 R 4 0.9 33 15-Aug-00 4.110228062 US R4 1.58 R 4 0.9...