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This patch initializes VMCB CR4 and shadow CR4 with 0 when VMCB is being constructed under nested paging mode. It complies with recent reset_to_realmode change in hvmloader. Signed-off-by: Wei Huang (wei.huang2@amd.com <mailto:wei.huang2@amd.com> ) _______________________________________________ Xen-devel mailing l...

Changes from v1 to v2: - Use a macro to replace the hardcode in patch 1/3. This patchset fixes issues about IA32_VMX_MISC MSR emulation, VMCS guest area synchronization about PAGE_FAULT_ERROR_CODE_MASK/PAGE_FAULT_ERROR_CODE_MATCH, and CR0/CR4 emulation. Please help to review and pull. Thanks, Dongxiao Dongxiao Xu (3): nested vmx: emulate IA32_VMX_MISC MSR nested vmx: synchronize page fault error code match and mask nested vmx: fix CR0/CR4 emulation xen/arch/x86/hvm/vmx/vvmx.c | 136 +++++++++++++++++++++++++++++-------...

...om> Index: clean-start/include/asm-x86_64/processor.h =================================================================== --- clean-start.orig/include/asm-x86_64/processor.h +++ clean-start/include/asm-x86_64/processor.h @@ -139,35 +139,6 @@ extern unsigned short num_cache_leaves; #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ /* - * Save the cr4 feature set we're using (ie - * Pentium 4MB enable and PPro Global page - * enable), so that any CPU's that boot up - * after us can get the correct flags. - */ -extern unsigned long mmu_cr4_features; - -static in...

...om> Index: clean-start/include/asm-x86_64/processor.h =================================================================== --- clean-start.orig/include/asm-x86_64/processor.h +++ clean-start/include/asm-x86_64/processor.h @@ -139,35 +139,6 @@ extern unsigned short num_cache_leaves; #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ /* - * Save the cr4 feature set we're using (ie - * Pentium 4MB enable and PPro Global page - * enable), so that any CPU's that boot up - * after us can get the correct flags. - */ -extern unsigned long mmu_cr4_features; - -static in...

...\ - : "=r" (tmpreg) \ - :: "memory"); \ - } while (0) - -/* - * Global pages have to be flushed a bit differently. Not a real - * performance problem because this does not happen often. - */ -#define __flush_tlb_global() \ - do { \ - unsigned int tmpreg, cr4, cr4_orig; \ - \ - __asm__ __volatile__( \ - "movl %%cr4, %2; # turn off PGE \n" \ - "movl %2, %1; \n" \ - "andl %3, %1; \n" \ - "movl %1, %%cr4; \n" \ - "mov...

...\ - : "=r" (tmpreg) \ - :: "memory"); \ - } while (0) - -/* - * Global pages have to be flushed a bit differently. Not a real - * performance problem because this does not happen often. - */ -#define __flush_tlb_global() \ - do { \ - unsigned int tmpreg, cr4, cr4_orig; \ - \ - __asm__ __volatile__( \ - "movl %%cr4, %2; # turn off PGE \n" \ - "movl %2, %1; \n" \ - "andl %3, %1; \n" \ - "movl %1, %%cr4; \n" \ - "mov...

...hanged, 7 insertions(+) > > diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S > index 08412f308de3..4622940134a5 100644 > --- a/arch/x86/kernel/head_64.S > +++ b/arch/x86/kernel/head_64.S > @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) > orl $X86_CR4_LA57, %ecx > 1: > #endif > + > + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE > + > + /* Early exception handling uses FSGSBASE on APs */ > + orl $X86_CR4_FSGSBASE, %ecx How is this supposed to work? Alternatives haven't run that e...

...hanged, 7 insertions(+) > > diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S > index 08412f308de3..4622940134a5 100644 > --- a/arch/x86/kernel/head_64.S > +++ b/arch/x86/kernel/head_64.S > @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) > orl $X86_CR4_LA57, %ecx > 1: > #endif > + > + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE > + > + /* Early exception handling uses FSGSBASE on APs */ > + orl $X86_CR4_FSGSBASE, %ecx How is this supposed to work? Alternatives haven't run that e...

...> > diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S > > index 08412f308de3..4622940134a5 100644 > > --- a/arch/x86/kernel/head_64.S > > +++ b/arch/x86/kernel/head_64.S > > @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) > > orl $X86_CR4_LA57, %ecx > > 1: > > #endif > > + > > + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE > > + > > + /* Early exception handling uses FSGSBASE on APs */ > > + orl $X86_CR4_FSGSBASE, %ecx > > How is this supposed...

From: Yang Zhang <yang.z.zhang@Intel.com> We exposed the xsave feature to guest, but we didn''t allow guest to set CR4.OSXSAVE when guest running in nested mode. This will cause win 7 guest fail to use XP mode. In this patch, we allow guest to set CR4.OSXSAVE in nested mode when it has the xsave feature. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> --- xen/arch/x86/hvm/vmx/vvmx.c | 8 +++++++- 1 fi...

...ble and enter protected page mode. In this step I also set x86_cr0_ne ( cr0.bit5) 4. call start_vmx. This start_vmx function is similar to the one in xen3.1.0 a. test cpuid with eax = 1. ecx.vmxe(bit5) is 1. b. Test IA32_FEATURE_CONTROL_MSR, result is 0x05, so bit 0 and bit 2 are both 1. c. Set cr4.vmxe (bit13) to 1 d. Call vmx_init_vmcs_config(). This function is the same as in xen3.1.0. e. Call vmxon, passing it the physical adderss calculated in step2, using the same op-code as xen f. stop vmx by calling vmxoff. Using "while(1)", I traced and found the GP exception happ...

...nel/head_64.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 08412f308de3..4622940134a5 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) orl $X86_CR4_LA57, %ecx 1: #endif + + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE + + /* Early exception handling uses FSGSBASE on APs */ + orl $X86_CR4_FSGSBASE, %ecx + +.Lstartup_write_cr4: movq %rcx, %cr4 /* Setup early boot stage 4-/5-level pagetables. */ --...

Changeset 21045: 7751288b1386 introduces a potential issue: CR4.MCE is enabled before mcheck_init() -- thought looks I don''t meet with an actual issue with this, we''d better fix it. Thanks, -- Dexuan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Fairly straightforward code motion in system.h into the sub-arch layer. Affected functionality include control register accessors, which are virtualizable but with great overhead due to the #GP cost; wbinvd, and most importantly, halt and interrupt control, which is non-virtualizable. Since read_cr4_safe can never fault on a VMI kernel (P5+ processor is required for VMI), we can omit the fault fixup, which does not play well with the VMI inline assembler, and just call read_cr4() directly. Note that shutdown_halt is unused, but provided in case there is really a use for it. See arch/i386/ker...

Fairly straightforward code motion in system.h into the sub-arch layer. Affected functionality include control register accessors, which are virtualizable but with great overhead due to the #GP cost; wbinvd, and most importantly, halt and interrupt control, which is non-virtualizable. Since read_cr4_safe can never fault on a VMI kernel (P5+ processor is required for VMI), we can omit the fault fixup, which does not play well with the VMI inline assembler, and just call read_cr4() directly. Note that shutdown_halt is unused, but provided in case there is really a use for it. See arch/i386/ker...

Hi everyone, I was trying to build a new machine but the system keeps rebooting. I used the lasted unstable version from xen-unstable.hg. I have tried with Fedora 16 (kernel 3.3.0-8) and Xubuntu 11.10 (3.0.0.17-generic). The output to my serial console is attached. Cheers, Francisco _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org

Hi, I''m trying to verify that the Xen I''m running is patched against the all the known published bugs. I''m running Fedora 7, which means I''m running Xen 3.1.2. I''ve checked the changelog in the Fedora package, and I can verify that all the bugs I''ve found are fixed except for one. http://www.securityfocus.com/bid/27219

...0:44:23 localhost kdm[25248]: X server termination timeout, killingSep 1 10:44:33 localhost kdm[25248]: X server is stuck in D state; leaving it aloneSep 1 10:44:33 localhost kdm[25248]: X server for display :0 cannot be started, session disabled # xm dmesg (XEN) domain.c:655:d0 Attempt to change CR4 flags 00002660 -> 000026e0(XEN) domain.c:655:d0 Attempt to change CR4 flags 00002660 -> 000026e0(XEN) domain.c:655:d0 Attempt to change CR4 flags 00002660 -> 000026e0(XEN) domain.c:655:d0 Attempt to change CR4 flags 00002660 -> 000026e0(XEN) domain.c:655:d0 Attempt to change CR4 flags 0...

...a student and recently work on my bachelor thesis. My goal is to write a little hypervisor. I''m not quite sure if this is the right mailing list, but i guess you''ll gonna tell me. i have two quick questions: 1. before i can use the vmxon instruction i do have to set vmxe flag in cr4 register. but what if some hypervisor is already running? is there a way to check if one is running?? 2. before i set the vmxe bit in cr4, i check if it is already enabled. i do this while my module gets loaded. but i observed a strange thing. sometimes the vmxe bit seems to be set while the othe...

...able way in which PVH is going to do AP bringup. Since we are running inside of a HVM container, PVH should only need to set flags, cr3 and user_regs in order to bring up a vCPU, the rest can be set once the vCPU is started using the bare metal methods. Additionally, the guest can also set cr0 and cr4, and those values will be appended to the default values set by Xen. Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Cc: George Dunlap <george.dunlap@eu.citrix.com> Cc: Mukesh Rathor <mukesh.rathor@oracle.com> Cc: Jan Beulich <JBeulich@suse.com> Cc: Tim Deegan <tim...