Displaying 3 results from an estimated 3 matches for "r3_1".
Did you mean:
r31
2018 Mar 22
1
TargetOpcode::KILL confusion
Hello,
Could someone please explain the semantics of TargetOpcode::KILL? Specifically, in this example, which register is killed? Would it be legal for operands 0 and 1 to refer to different registers?
128B %R3<def> = KILL %R3, %R3_1<imp-use>, %R3_23<imp-use>
(In my out-of-tree target, %R3 is a <4xi32> register, %R3_1 is an i32 sub-register of %R3, and %R3_23 is a <2xi32> sub-register of %R3).
Thanks,
Nick
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://l...
2005 Jul 27
3
[LLVMdev] How to define complicated instruction in TableGen (Direct3D shader instruction)
...gt; {}
def SM: SourceModifier ;
def ADD<0x01, (ops
GPR:$dest, ops WM:$wm, IM:$im,
GPR:$src0, SW:$sw0, SM:$sm0,
GPR:$src1, SW:$sw1 SM:$sm1 ), ... >
2. add llvm intrinsics:
; add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz
r1_1 = llvm.bias( r1_0 )
r1_2 = llvm.shuffle( xxyy )
r3_1 = llvm.x2( r3_0 )
r3_2 = llvm.shuffle( zzzz )
r0_0 = add r1_2, r3_2
r0_1 = llvm.sature( r0_0 )
r0_2 = llvm.select( a )
but it makes the implementing the instruction selector very diffifult.
in this example, llvm.select() and llvm.sature() are encountered frist
(bootm-up), but they must be...
2005 Jul 29
0
[LLVMdev] How to define complicated instruction in TableGen (Direct3D shader instruction)
...01, (ops
> GPR:$dest, ops WM:$wm, IM:$im,
> GPR:$src0, SW:$sw0, SM:$sm0,
> GPR:$src1, SW:$sw1 SM:$sm1 ), ... >
>
> 2. add llvm intrinsics:
>
> ; add_sat r0.a, r1_bias.xxyy, r3_x2.zzzz
> r1_1 = llvm.bias( r1_0 )
> r1_2 = llvm.shuffle( xxyy )
> r3_1 = llvm.x2( r3_0 )
> r3_2 = llvm.shuffle( zzzz )
> r0_0 = add r1_2, r3_2
> r0_1 = llvm.sature( r0_0 )
> r0_2 = llvm.select( a )
>
> but it makes the implementing the instruction selector very diffifult.
> in this example, llvm.select() and llvm.sature() are encountered...