search for: r31

Sadly the latest optimization broke completely everything. The asm code isn't gas compliant. the libFLAC linker script has a typo, disabling the asm optimization and/or altivec won't let a correct build anyway. Instant fixes for the asm stuff: sed -i -e"s:;:\#:" on the lpc_asm.s to load address instead of addis+ori you could use lis and la and PLEASE use the @l(register)

...e residual) ; I haven't yet run this through simg4, so there may be some avoidable stalls, ; and there may be a somewhat more clever way to do the outer loop ; the branch mechanism may prevent dynamic loading; I still need to examine ; this issue, and there may be a more elegant method stmw r31,-4(r1) addi r9,r1,-28 li r31,0xf andc r9,r9,r31 ; for quadword-aligned stack data slwi r6,r6,2 ; adjust for word size slwi r4,r4,2 add r4,r4,r8 ; r4 = data+data_len mfspr r0,256 ; cache old vrsave addis r31,0,hi16(0xfffffc00) ori r31,r31,lo16(0xfffffc00) mtspr 256,r31 ; declare VRs in...

...s should get cleaned up. [Clearly 17 shaders > disagree...] Is this just a side-effect of the fact that we don't run > the opts to a fixed point? It is a second mov that causes a problem for later folding in the imm, here output of a testshader[1]: 0: nop u32 %r56 (0) 1: ld u32 %r31 c0[0x0] (0) 2: ld u32 %r37 c0[0x140] (0) 3: mov u32 %r38 0x00000000 (0) 4: mov u32 %r39 0x3f800000 (0) 5: mad f32 %r40 %r37 %r38 %r39 (0) 6: mad f32 %r44 %r37 %r38 %r38 (0) 7: add f32 %r53 %r31 %r40 (0) 8: add f32 %r54 %r31 %r44 (0) 9: add f32 %r57 %r56 %r44 (0) Constantfo...

...2 = 1; \ + ;; \ + /* note: clears both vpsr.i and vpsr.ic! */ \ + st1 [clob0] = clob2; \ + st4 [clob1] = r0; \ + ;; + +#define RSM_PSR_DT \ + XEN_HYPER_RSM_PSR_DT + +#define SSM_PSR_DT_AND_SRLZ_I \ + XEN_HYPER_SSM_PSR_DT + +#define BSW_0(clob0, clob1, clob2) \ + ;; \ + /* r16-r31 all now hold bank1 values */ \ + mov clob2 = ar.unat; \ + movl clob0 = XSI_BANK1_R16; \ + movl clob1 = XSI_BANK1_R16 + 8; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r16, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r17, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r1...

...8    R12         R23 9    R13         R23                          If instead of two rates, suppose there are three rates, I will have to modify my code as   data_label = expand.grid(c("R11", "R12", "R13"), c("R21", "R23", "R23"), c("R31", "R32", "R33"))   If I define say   n = no_of_rates  # I will be taking this figure from some otehr csv file.   My PROBLEM = B is how do I write the above code pertaining to data_label in terms of 'n'.   ## __________________________________________________________...

...er 913, set 1, 3, and 4 would be part of my "zeros" data.frame as they appear with no record.t 6, such that no species were observed in this survey unit. > head(RV09) record.t trip set month stratum NAFO unit.area time dur.set distance 585 5 913 1 10 351 3O R31 1044 17 9 586 5 913 2 10 351 3O R31 1440 17 9 587 6 913 2 10 351 3O R31 1440 17 9 588 5 913 3 10 340 3O Q31 1800 18 9 589 5 913 4 10 340 3O Q32 2142...

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

...> However, Linux and Darwin do not have the same set >> of non-callee saved registers. I don't know how to make the if(isDarwin) test >> in here >> > > Take a look at ARM/ARMRegisterInfo.td for an example of this. > > Great, thx for the hint >> 3) R31, which replaces R1 as stack pointer when there is a dynamic allocation >> in a method, must be seen as a callee-saved register and must not be saved >> and restored like it is actually for Darwin. I don't know how to specify >> that, when there is a dynamic allocation, R31...

...PredicateInstruction(), which is employed also in IfConversion.cpp. More exactly I'm trying to use a pseudo-instruction that will get translated to a sequence of 4 MachineInstr, namely: // These 4 instructions replace the pseudo-instruction I use for LLVM's VSELECT R31 = OR srcVselectFalse, srcVselectFalse WHEREEQ R31 = OR srcVselectTrue, srcVselectTrue ENDWHERE I plan to do this as early as possible, in a pass registered in addInstSelector() normally, which gets executed immediately after the first scheduling phase. If an...

...you add -run-pass if-converter, you'll get: # After If Converter # Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs BB#0: %R0<def> = L2_ploadruhf_io %P0<undef>, %R0<undef>, 0, %R0<imp-use> PS_storerhabs 0, %R0 PS_jmpret %R31<kill>, %PC<imp-def> # End machine code for function fred. *** Bad machine code: Using an undefined physical register *** - function: fred - basic block: BB#0 (0x411e8e8) - instruction: %R0<def> = L2_ploadruhf_io - operand 4: %R0<imp-use> LLVM ERROR: Found 1 machine c...

...erand. I'm not sure if this is the correct way to do this, but it works. 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved registers. However, Linux and Darwin do not have the same set of non-callee saved registers. I don't know how to make the if(isDarwin) test in here 3) R31, which replaces R1 as stack pointer when there is a dynamic allocation in a method, must be seen as a callee-saved register and must not be saved and restored like it is actually for Darwin. I don't know how to specify that, when there is a dynamic allocation, R31 must be added to the set o...

...cit-def %pc bb.1: successors: %bb.3 %r0 = L2_loadruh_io undef %r0, 0 PS_storerhabs 0, killed %r0 J2_jump %bb.3, implicit-def %pc bb.2: successors: %bb.3 PS_storerhabs 0, undef %r0 J2_jump %bb.3, implicit-def %pc bb.3: PS_jmpret killed %r31, implicit-def %pc ... Run: llc -march=hexagon -run-pass branch-folder test.mir -o - We get an invalid code: body: | bb.0: successors: %bb.1(0x40000000), %bb.2(0x40000000) J2_jumpt undef %p0, %bb.2, implicit-def %pc bb.1: successors: %bb.2(0x80000000) %r0 = L2_loadruh...

...haders >> disagree...] Is this just a side-effect of the fact that we don't run >> the opts to a fixed point? > > > It is a second mov that causes a problem for later folding in the imm, here > output of a testshader[1]: > > 0: nop u32 %r56 (0) > 1: ld u32 %r31 c0[0x0] (0) > 2: ld u32 %r37 c0[0x140] (0) > 3: mov u32 %r38 0x00000000 (0) > 4: mov u32 %r39 0x3f800000 (0) > 5: mad f32 %r40 %r37 %r38 %r39 (0) > 6: mad f32 %r44 %r37 %r38 %r38 (0) > 7: add f32 %r53 %r31 %r40 (0) > 8: add f32 %r54 %r31 %r44 (0) > 9: add f3...

...does not select it. >> > > Okay, I'm not sure. If you describe the constraints better, perhaps Jim > or Evan will have an idea :) > Well i believe the algorithm that finds clobbered registers does not look at the epilogue and prologue, and therefore does not select R31. Maybe all I need to do is to explicitly add R31 as a clobbered register when it is used as a frame pointer. But I need some help to do that. Thx, Nicolas

...e multiple targets using the same ABI, it doesn't make sense to have os-specific aspects. An example of an OS-specific aspect: cygwin and mingw on x86 use the same ABI, however, mingw refers to longjmp as "longjmp" and cygwin refers to it as "_longjmp". >>> 3) R31, which replaces R1 as stack pointer when there is a dynamic allocation >>> in a method, must be seen as a callee-saved register and must not be saved >>> and restored like it is actually for Darwin. I don't know how to specify >>> that, when there is a dynamic allocat...

...stw 0, 4(1) stwu 1, -16(1) lis 3, .Lstr at ha mr 31, 1 la 3, .Lstr at l(3) bl puts li 3, 0 addi 1, 1, 16 lwz 0, 4(1) lwz 31, -4(1) mtlr 0 blr By the strict letter of the 32-bit ABI, the save and restore of r31 at a negative offset of r1 is verboten. The ABI states the the stack space below the stack pointer is declared as volatile. I actually debugged a similar problem way back in my Blue Gene/L days, where gcc had a bug and was doing the same thing. We ended up taking a signal between the restore of t...

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

...cit-def %pc bb.1: successors: %bb.3 %r0 = L2_loadruh_io undef %r0, 0 PS_storerhabs 0, killed %r0 J2_jump %bb.3, implicit-def %pc bb.2: successors: %bb.3 PS_storerhabs 0, undef %r0 J2_jump %bb.3, implicit-def %pc bb.3: PS_jmpret killed %r31, implicit-def %pc ... If the merging process produced this intermediate code (I stripped some unimportant pieces): bb.1: %r0 = L2_loadruh_io undef %r0, 0 J2_jump %bb.tail bb.2: J2_jump %bb.tail bb.tail: liveins: %r0 PS_storerhabs 0, killed %r0...