search for: r32c

...info w/o tblgen bitching up a storm about the "$" or the extra "bi" operands? - Immediates in a pattern: To move one register to another involves using the 3-operand OR instruction, but how do I encode an immediate w/o a type inference contradiction? def : Pat<(set R32C:$rDest, R32C:$rSrc), (ORIr32 R32C:$rSrc, 0)>; Thanks for the clue!

...!strconcat("bi ", !strconcat("$", "lr")). > > - Immediates in a pattern: To move one register to another involves > using the 3-operand OR instruction, but how do I encode an immediate > w/o a type inference contradiction? > > def : Pat<(set R32C:$rDest, R32C:$rSrc), > (ORIr32 R32C:$rSrc, 0)>; I am not sure what you mean. By 3-operand, you mean 2 source operand and 1 destination. I don't think the error you are seeing have anything to do with the immediate. For a def : Pat pattern, you don't need to specify...

I've got an instruction that has the following pattern (R32C is the 32-bit register class): (set R32C:$rT, (or (and R32C:$rA, R32C:$rC), (and R32C:$rB, (not R32C:$rC)))) tblgen generates the following variants (I've dropped the R32C for brevity): (or (and $rA, $rC), (and $rB, (not $rC))) # original (or (and $rA, $rC), (and (no...

...t("$", "lr")). Yep, $$ should work. >> - Immediates in a pattern: To move one register to another involves >> using the 3-operand OR instruction, but how do I encode an immediate >> w/o a type inference contradiction? >> >> def : Pat<(set R32C:$rDest, R32C:$rSrc), >> (ORIr32 R32C:$rSrc, 0)>; You current cannot specify move patterns in the .td file. You specify them with XXXRegisterInfo::copyRegToReg and XXXInstrInfo::isMoveInstr. See the PPC or Sparc backend for some simple examples. -Chris -- http://nondot.or...

I overrode getInstrLatency and did some printing to see what is available there. It looks like the registers are still virtual at that point when getInstrLatency is called - is that correct? (we needed to make some decisions based on actual registers that have been assigned since some registers are reserved as address space pointers and we could vary the latency based on which address space