search for: r30

I see instcombine doing something I'm not sure is right. Incoming, I have this: %r29 = ptrtoint [71 x i64]* %"t$3" to i64 ; <i64> [#uses=1] %r30 = inttoptr i64 %r29 to i64* ; <i64*> [#uses=1] store i64 72057594037927936, i64* %r30, align 8 Outgoing, I have this: %r30 = getelementptr [71 x i64]* %"t$3", i32 0, i32 0 ; <i64*> [#uses=1] store i64 72057594037927936, i64* %r30, align 16 I believe the alignment on th...

...clob1] = r25, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r26, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r27, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r28, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r29, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r30, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r31, 16; \ + ;; \ + mov clob1 = ar.unat; \ + movl clob0 = XSI_B1NAT; \ + ;; \ + st8 [clob0] = clob1; \ + mov ar.unat = clob2; \ + movl clob0 = XSI_BANKNUM; \ + ;; \ + st4 [clob0] = r0 + + + /* FIXME: THIS CODE IS NOT NaT S...

...at location [SP-84] DBG_VALUE <fi#2>, 0, !"fooBar"; line no:299 ************************** Clearly, the FI in question is at an offset of -84 from the SP at entry to the function i.e. FP - 84. So I remove the FI by changing the instruction to. ************************** DBG_VALUE %R30, -84, !"fooBar"; line no:299 ************************** (R30 is the frame pointer register in Hexagon.) So, logically we have moved from frame indices to actually base + offset representation. However the assembly printer, while trying to emit debug info, sticks to the frame index repre...

...fi#2>, 0, !"fooBar"; line no:299 > ************************** > > Clearly, the FI in question is at an offset of -84 from the SP at entry to > the function i.e. FP - 84. So I remove the FI by changing the instruction > to. > ************************** > DBG_VALUE %R30, -84, !"fooBar"; line no:299 > ************************** > (R30 is the frame pointer register in Hexagon.) The offset field on a DBG_VALUE instruction refers to the user variable, not the first register argument. Your DBG_VALUE above is saying that fooBar[-84] can be found in %R3...

Revision: 30 Author: freyfogle Date: Sun Sep 20 06:26:44 2009 Log: jslint now passing for google and googlev3 http://code.google.com/p/mapstraction/source/detail?r=30 Modified: /trunk/build.xml /trunk/source/mxn.google.core.js /trunk/source/mxn.googlev3.core.js ======================================= --- /trunk/build.xml Sun Sep 20 06:13:41 2009 +++ /trunk/build.xml Sun Sep 20 06:26:44

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested

...RC:%vreg21 G8RC_and_G8RC_NOX0:%vreg6 560B BLR8 %LR8<imp-use>, %RM<imp-use>, %X3<imp-use> -- Due to all of the register pressure built up by those loads we are forced to spill. Here is the final assembly. -- # BB#0: # %entry std r30, -16(r1) # 8-byte Folded Spill ld r5, 0(r3) ld r6, 0(r4) ld r7, 8(r3) ld r8, 8(r4) ld r9, 16(r3) ld r10, 16(r4) ld r11, 24(r3) ld r0, 32(r3) ld r12, 24(r4) ld r30, 32(r4) ld r3, 40(r3) ld...

...// encoding: [A,0x63'A',0x40'A',0x15'A',0x00,0xc0,0x63,0x70] // fixup A - offset: 0, value: .LBB0_3, kind: fixup_Hexagon_B9_PCREL // %bb.4: // %while.end { r31:30 = dealloc_return(r30):raw } // encoding: [0x1e,0xc0,0x1e,0x96] .LBB0_5: // %while.body.rtli { call memmove r1:0 = combine(r2,r1) r2 = #400 } // encoding: [A,0x40'A',A,0x5a'A',0x00,0x41,0x02,0xf5,0x02,0xf2...

...Predecessors according to CFG: BB#1 %vreg61<def> = LDrih_indexed %vreg56, 3134; IntRegs:%vreg61,%vreg56 %vreg62<def> = LDriuh_indexed %vreg56, 680; IntRegs:%vreg62,%vreg56 %R1<def> = TFRI 1431655766 ADJCALLSTACKDOWN 0, %R29<imp-def>, %R30<imp-def>, %R31<imp-use>, %R30<imp-use>, %R29<imp-use> %vreg304:subreg_loreg<def,read-undef> = ADDri_SUBr_V4 %vreg62, 5, %vreg61; DoubleRegs:%vreg304 IntRegs:%vreg62,%vreg61 %vreg519<def> = TFRI 3148; IntRegs:%vreg519 %vreg523<def&g...

...lowing error message during the boot process: EXT3-fs: unable to read superblock mount:error 22 mounting ext3 flags Freeing unused kernel memory: 260k freed Kernel panic: No init found. Try passing init = option to kernel I was using RedHat 7.3 when this problem appeared. My machine is a ThinkPad R30 Intel Celeron 900 MHz. I used "linux rescue", to get access to my hard drive data. I changed ext3 tags to ext2 in my /etc/fstab file but it didn't work. I installed RedHat 8.0 but I was still receiving the same error message even if I formatted the / partition during the installat...

...gt; eventually get you to the first "lis". > > Getting from use-node to def-node is a single step. > Visiting other def/use nodes from the same statement, given a def-node is > linear in terms of number of def/use nodes in that statement. > > If you want to rematerialize r30, then the whole sequence would need to > use r30 (instead of r3). This is because r3 may not be available at the > point where r30 is to be rematerialized. Finding out if r3 is live or not > is also possible, but would require extra analysis. > > Getting an instruction, given an RDF...

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place

...0x15'A',0x00,0xc0,0x63,0x70] // fixup A - offset: 0, value: .LBB0_3, kind: fixup_Hexagon_B9_PCREL // %bb.4: // %while.end { r31:30 = dealloc_return(r30):raw } // encoding: [0x1e,0xc0,0x1e,0x96] .LBB0_5: // %while.body.rtli { call memmove r1:0 = c...

Hi, Compiling for both x86 and ARM with llc aborts after this pass. I have a simple helloworld.c program. I am attaching the .ll file created by: *clang -O3 -g -emit-llvm hello.c -c -o hello.bc* *llvm-dis hello.bc* Thanks again for the response! Shruti On Mon, May 19, 2014 at 1:28 AM, Tobias Grosser <tobias at grosser.es> wrote: > On 19/05/2014 00:54, shruti padmanabha wrote: >

...warfRegNum<[25]>; def R26 : DLXR<26, "r26">, DwarfRegNum<[26]>; def R27 : DLXR<27, "r27">, DwarfRegNum<[27]>; def R28 : DLXR<28, "r28">, DwarfRegNum<[28]>; def R29 : DLXR<29, "r29">, DwarfRegNum<[29]>; def R30 : DLXR<30, "r30">, DwarfRegNum<[30]>; def R31 : DLXR<31, "r31">, DwarfRegNum<[31]>; // Register classes def DLXRegs : RegisterClass<"DLX", [i32], 32, // Volatile [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R...

...13: 0x00000000 r14: 0x000021bc r15: 0x00000000 r16: 0xbffffcb4 r17: 0x00000001 r18: 0x00000000 r19: 0x000016d4 r20: 0x00000000 r21: 0x00000000 r22: 0x00000000 r23: 0x00000000 r24: 0x8fe4b3d8 r25: 0x00000002 r26: 0x00000002 r27: 0x00000000 r28: 0x00001610 r29: 0x00000000 r30: 0x8fe484d8 r31: 0x8fe09ecc

...:59 +0400 (Втр, 01 Авг 2006) | 1 line Moved for versioning. ------------------------------------------------------------------------ r31 | jlaskey | 2006-08-01 00:58:54 +0400 (Втр, 01 Авг 2006) | 1 line Moved for versioning. ------------------------------------------------------------------------ r30 | jlaskey | 2006-08-01 00:58:50 +0400 (Втр, 01 Авг 2006) | 1 line > What command generates it? "svn log" Thanks. -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University.

...= add i32 %sub, %d ; <i32> [#uses=1] ret i32 %add4 } which lowers to this assembler code (note: args arrive in r1..r12, and results are returned in r1..r3.): foo: add r2,r1 ### add r1,r2 is better sub r2,r3 mov r1,r2 ### unnecessary!! add r1,r4 jmp [r30] .end foo The mov insn would be unnecessary if the operand order for the first add were reversed. For this function, GCC does the right thing. Is there some optimizer knob I'm not turning properly? In more complex cases, GCC does poorly with two-address operand choices and so bloats...