search for: r3

...nop The two comparisons are very similar. For the Microblaze, I get: signed long long: main: .frame r19,40,r15 .mask 0x80000 addik r1, r1, -40 swi r19, r1, 4 add r19, r1, r0 swi r0, r19, 8 addik r3, r0, 100 swi r3, r19, 20 swi r0, r19, 16 addik r3, r0, -2147483648 swi r3, r19, 24 swi r0, r19, 28 lwi r4, r19, 16 xor r3, r4, r3 lwi r4, r19, 20 or r3, r4, r3...

...: - mflr %r11 /* save return address */ - mfcr %r12 /* save condition register */ - mr %r10,%r1 /* save stack pointer */ - mr %r9,%r2 /* save GPR2 (not needed) */ - stmw %r9,0(%r3) /* save r9..r31 */ - li %r3,0 /* indicate success */ - blr /* return */ + mflr %r11 /* save return address */ + mfcr %r12 /* save condition register */ + std %r2,0(%r3) /* save TOC pointer (not needed) */ + stdu %r1...

I have two data frames. Suppose the first has rows r1 r2 r3 and the second has rows R1 R2 R3 I'd like to generate the data frame: r1 R1 r1 R2 r1 R3 r2 R1 r2 R2 r2 R3 r3 R1 r3 R2 r3 R3 How would I go about doing this? I'm sure there's a clean way to do it but I find myself thinking in loo...

..._r17; + unsigned long __r18; + unsigned long __r19; + unsigned long __r20; + unsigned long __r21; + unsigned long __r22; + unsigned long __r23; + unsigned long __r24; + unsigned long __r25; + unsigned long __r26; + unsigned long __r27; + unsigned long __r28; + unsigned long __r29; + unsigned long __r30; + unsigned long __r31; +}; + +typedef struct __jmp_buf jmp_buf[1]; + +#endif /* _SETJMP_H */ diff --git a/usr/include/arch/ppc64/klibc/archsignal.h b/usr/include/arch/ppc64/klibc/archsignal.h new file mode 100644 index 0000000..2c4cef0 --- /dev/null +++ b/usr/include/arch/ppc64/klibc/archsigna...

...; > struct foo { > > struct foo *next; > > }; > > struct foo a; > > struct foo b; > > struct foo c = { &a }; > > struct foo d = { &b }; > > struct foo x = { &c }; > > struct foo y = { &d }; > > struct foo *r1, *r2, *r3; > > > > void cpu0(void) > > { > > WRITE_ONCE(x.next, &y); > > } > > > > void cpu1(void) > > { > > r1 = lockless_dereference(x.next); > > WRITE_ONCE(r1->next, &x); > > } > > > > void cpu2(void)...

...; > struct foo { > > struct foo *next; > > }; > > struct foo a; > > struct foo b; > > struct foo c = { &a }; > > struct foo d = { &b }; > > struct foo x = { &c }; > > struct foo y = { &d }; > > struct foo *r1, *r2, *r3; > > > > void cpu0(void) > > { > > WRITE_ONCE(x.next, &y); > > } > > > > void cpu1(void) > > { > > r1 = lockless_dereference(x.next); > > WRITE_ONCE(r1->next, &x); > > } > > > > void cpu2(void)...

...e performance is optimized) by swapping the 2nd and 3rd operands: add r1, r1, r2 # r1 <- r1 + r2 There are four banks and the formula to figure out which bank a register is in is just: r%4 Which brings me to tablegen: We've got this in our specialized ArchInstrInfo.td: // r1 = r2 op r3 // class ArithOp_RR< bits<7> op, string instr_asm, SDNode opNode, OperandInfo info, InstrItinClass itin > : FR3< op, (outs info.regClass:$r1), (ins info.regClass:$r2, info.regClass:$r3),...

...302 r1 0.009489 > 204 11157 304 r1 0.010142 > 403 11158 300 r1 0.026999 > 404 11158 302 r1 0.029612 > 405 11158 304 r1 0.030271 > 604 11159 300 r1 0.032784 > 66934 38711 300 r3 0.062081 > 66935 38711 302 r3 0.065137 > 66936 38711 304 r3 0.067092 > 67135 38712 300 r3 0.029389 > 67136 38712 302 r3 0.030192 > 67137 38712 304 r3 0.030860 > 67336 38993 300 r3 0.045720 &g...

...> + leaq tab_off(%rip), RBASE; \ >> + movl (RBASE,reg_i,4), reg_o; >> + >> +#define round_xor(tab_off, reg_i, reg_o) \ >> + leaq tab_off(%rip), RBASE; \ >> + xorl (RBASE,reg_i,4), reg_o; >> + >> #define round(TAB,OFFSET,r1,r2,r3,r4,r5,r6,r7,r8,ra,rb,rc,rd) \ >> movzbl r2 ## H,r5 ## E; \ >> movzbl r2 ## L,r6 ## E; \ >> - movl TAB+1024(,r5,4),r5 ## E;\ >> + round_mov(TAB+1024, r5, r5 ## E)\ >> movw r4 ## X,r2 ## X; \ >> - movl T...

...> + leaq tab_off(%rip), RBASE; \ >> + movl (RBASE,reg_i,4), reg_o; >> + >> +#define round_xor(tab_off, reg_i, reg_o) \ >> + leaq tab_off(%rip), RBASE; \ >> + xorl (RBASE,reg_i,4), reg_o; >> + >> #define round(TAB,OFFSET,r1,r2,r3,r4,r5,r6,r7,r8,ra,rb,rc,rd) \ >> movzbl r2 ## H,r5 ## E; \ >> movzbl r2 ## L,r6 ## E; \ >> - movl TAB+1024(,r5,4),r5 ## E;\ >> + round_mov(TAB+1024, r5, r5 ## E)\ >> movw r4 ## X,r2 ## X; \ >> - movl T...

...re entirely complicated and different. The port has a 5 stage pipeline where the result of instruction can only be used at stage 3 and 5 only whereas load and store instructions require 4 cycles. That means that if there was a code such as code 1 code 2 lwi r3, r0, 4 addik r3, r4, 5 cmp r4, r3, 5 swi r3, r0, 12 swi r3, r0, 16 would cause cmp and swi r3,r0,12 to use the old value of r3. It should be lwi r3, r0, 4 addik r3, r4, 5 nop...

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/shader/Makefile | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/shader/Makefile b/src/shader/Makefile index 46658e9..2d789be 100644 --- a/src/shader/Makefile +++ b/src/shader/Makefile @@ -24,20 +24,21 @@ NVF0_SHADERS = xfrm2nvf0.vpc \ videonvf0.fpc SHADERS = $(NVC0_SHADERS)

...bspeex.so.1 #2 0x4002bec0 in nb_encode () from ./libspeex.so.1 #3 0x40036c84 in speex_encode_int () from ./libspeex.so.1 #4 0x00008d68 in main () (gdb) disassemble Dump of assembler code for function open_loop_nbest_pitch: ... skipped... 0x40030300 <open_loop_nbest_pitch+620>: add r0, r3, r8 0x40030304 <open_loop_nbest_pitch+624>: ldrsh r3, [r0] 0x40030308 <open_loop_nbest_pitch+628>: mov r3, r3, lsl #1 0x4003030c <open_loop_nbest_pitch+632>: strh r3, [r0], #2 0x40030310 <open_loop_nbest_pitch+636>: add r6, r6, #1 ; 0x1 0x40030314 <open_...

Dear list, I have been studying R and I would like the aid of more experienced to solve the problems of the analysis below: r = gl(3, 8, label = c('r1', 'r2', 'r3')) e = rep(gl(2, 4, label = c('e1', 'e2')), 3) y = c(26.2, 26.0, 25.0, 25.4, 24.8, 24.6, 26.7, 25.2, 25.7, 26.3, 25.1, 26.4, 19.6, 21.1, 19.0, 18.6, 22.8, 19.4, 18.8, 19.2, 19.8, 21.4, 22.8, 21.3) df = data.frame(r, e, y) aux = sort(rep(letters[1:6], 4)) #auxiliary vari...

...to a load to get WRC. Plus the levels of indirection definitely didn't match up, did they? struct foo { struct foo *next; }; struct foo a; struct foo b; struct foo c = { &a }; struct foo d = { &b }; struct foo x = { &c }; struct foo y = { &d }; struct foo *r1, *r2, *r3; void cpu0(void) { WRITE_ONCE(x.next, &y); } void cpu1(void) { r1 = lockless_dereference(x.next); WRITE_ONCE(r1->next, &x); } void cpu2(void) { r2 = lockless_dereference(y.next); r3 = READ_ONCE(r2->next); } In this case, it is legal to end the run with: r1 ==...

...to a load to get WRC. Plus the levels of indirection definitely didn't match up, did they? struct foo { struct foo *next; }; struct foo a; struct foo b; struct foo c = { &a }; struct foo d = { &b }; struct foo x = { &c }; struct foo y = { &d }; struct foo *r1, *r2, *r3; void cpu0(void) { WRITE_ONCE(x.next, &y); } void cpu1(void) { r1 = lockless_dereference(x.next); WRITE_ONCE(r1->next, &x); } void cpu2(void) { r2 = lockless_dereference(y.next); r3 = READ_ONCE(r2->next); } In this case, it is legal to end the run with: r1 ==...

Hi, Compiling attached test-case, which is reduced version of of uECC_shared_secret from tinycrypt library [1], with --target=arm-linux-gnueabi -march=armv6-m -Oz -S results in reloading of register holding function's address before every call to blx: ldr r3, .LCPI0_0 blx r3 mov r0, r6 mov r1, r5 mov r2, r4 ldr r3, .LCPI0_0 blx r3 ldr r3, .LCPI0_0 mov r0, r6 mov r1, r5 mov r2, r4 blx r3 .LCPI0_0: .long fo...

Hi, I'm trying to get speex working on an ARM board (ARM926EJ-Sid(wb) core, ARM 5TE architecture) and getting segfaults if build with "--enable-fixed-point --enable-arm5e-asm" options. If I use just "--enable-fixed-point", then it runs fine, but once I add "--enable-arm5e-asm" it start crashing (I use testenc to test it). Further investigation showed, that it

https://bugs.freedesktop.org/show_bug.cgi?id=78161 Priority: medium Bug ID: 78161 Assignee: nouveau at lists.freedesktop.org Summary: [NV96] Artifacts in output of fragment program containing not unrolled loops with conditional break Severity: normal Classification: Unclassified OS: Linux (All)

...p)); + DEFINE(OFFSET_VLR, offsetof(struct cpu_info, vlr)); + BLANK(); + DEFINE(OFFSET_VCPU_R0, offsetof(struct vcpu_guest_context, r0)); + DEFINE(OFFSET_VCPU_R1, offsetof(struct vcpu_guest_context, r1)); + DEFINE(OFFSET_VCPU_R2, offsetof(struct vcpu_guest_context, r2)); + DEFINE(OFFSET_VCPU_R3, offsetof(struct vcpu_guest_context, r3)); + DEFINE(OFFSET_VCPU_R4, offsetof(struct vcpu_guest_context, r4)); + DEFINE(OFFSET_VCPU_R5, offsetof(struct vcpu_guest_context, r5)); + DEFINE(OFFSET_VCPU_R6, offsetof(struct vcpu_guest_context, r6)); + DEFINE(OFFSET_VCPU_R7, offsetof(struct vcpu...