search for: r27

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2007 Mar 21
2
home_location or smth like that
hi dovecot list help me please dovecot-1.0.r27 exim lda virtual users in ldap base i decided to start using the sieve pluging so i have to make the homes (now my homeDirectory in ldapbase is /nonexistent). there is a lot of users, so i dont wonna to make changes in every ldap record + imho the hard link to userhome in ldap - its a not good...
2011 Jul 03
0
[LLVMdev] DLX backend
...warfRegNum<[22]>; def R23 : DLXR<23, "r23">, DwarfRegNum<[23]>; def R24 : DLXR<24, "r24">, DwarfRegNum<[24]>; def R25 : DLXR<25, "r25">, DwarfRegNum<[25]>; def R26 : DLXR<26, "r26">, DwarfRegNum<[26]>; def R27 : DLXR<27, "r27">, DwarfRegNum<[27]>; def R28 : DLXR<28, "r28">, DwarfRegNum<[28]>; def R29 : DLXR<29, "r29">, DwarfRegNum<[29]>; def R30 : DLXR<30, "r30">, DwarfRegNum<[30]>; def R31 : DLXR<31, "r31&quo...
2009 Aug 31
1
Upgrading Asterisk in Trixbox installation
Hi, My Trixbox 2.8.0.1 installation includes the following Asterik version: 1.6.0.9-samy-r27 I am having some problems with it and I think they might be solved if I use the latest Asterisk version. Is it a good idea to update Asterisk in Trixbox externally ? Is it safe ? If so, which version should I prefer ? 1.6.1.5 or 1.6.0.14 ? Thanks, ilker -------------- next part -------------- An...
2004 Mar 02
1
Immediate crash on Mac OS X 10.2.8
...10: 0xbffff78b r11: 0x00000026 r12: 0x8fe71ac7 r13: 0x00000000 r14: 0x000021bc r15: 0x00000000 r16: 0xbffffcb4 r17: 0x00000001 r18: 0x00000000 r19: 0x000016d4 r20: 0x00000000 r21: 0x00000000 r22: 0x00000000 r23: 0x00000000 r24: 0x8fe4b3d8 r25: 0x00000002 r26: 0x00000002 r27: 0x00000000 r28: 0x00001610 r29: 0x00000000 r30: 0x8fe484d8 r31: 0x8fe09ecc
2009 Aug 31
1
Asterisk MWI issue
...i, I am using Asterisk personally at home. My SIP client (SPA 3000) supports MWI with SIP NOTIFY messages. With a previous version of Asterisk I had no problems with MWI. But now I am using the following version which comes with Trixbox 2.8.0.1, and I have problems with MWI. Asterisk 1.6.0.9-samy-r27 Problem description: When a voicemail is left on the extension, a SIP NOTIFY message is sent to my SIP client and the MWI is received ok. This is good. But when I delete all Voicemail through AMPortal, SIP NOTIFY message notifying that there is no voicemail left is not sent to the client. Normally...
2008 Sep 08
2
[LLVMdev] Overzealous PromoteCastOfAllocation
...] %V.in8.mask = and i32 %A12.ins, -65536 ; <i32> [#uses=1] %B9.ins = or i32 %V.in8.mask, %B9 ; <i32> [#uses=2] %R14 = lshr i32 %B9.ins, 16 ; <i32> [#uses=1] %R15 = trunc i32 %R14 to i16 ; <i16> [#uses=1] %R27 = trunc i32 %B9.ins to i16 ; <i16> [#uses=1] call void @bar( i16 %R15, i16 %R27 ) call void @empty( ) ret void } However, when I run -deadargelim -die -scalarrepl directly on the original code, I get the result I expect: define void @foo(i16 %A, i16 %B) { entry:...
2008 Feb 26
8
[PATCH 0/8] RFC: ia64/xen TAKE 2: paravirtualization of hand written assembly code
Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place
2008 Feb 26
8
[PATCH 0/8] RFC: ia64/xen TAKE 2: paravirtualization of hand written assembly code
Hi. I rewrote the patch according to the comments. I adopted generating in-place code because it looks the quickest way. The point Eddie wanted to discuss is how to generate code and its ABI. i.e. in-place generating v.s. direct jump v.s. indirect function call Indirect function call doesn't make sense because ivt.S is compiled multi times. And it is up to pv instances to choose in-place
2008 Feb 25
6
[PATCH 0/4] ia64/xen: paravirtualization of hand written assembly code
Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested
2008 Feb 25
6
[PATCH 0/4] ia64/xen: paravirtualization of hand written assembly code
Hi. The patch I send before was too large so that it was dropped from the maling list. I'm sending again with smaller size. This patch set is the xen paravirtualization of hand written assenbly code. And I expect that much clean up is necessary before merge. We really need the feed back before starting actual clean up as Eddie already said before. Eddie discussed how to clean up and suggested
2010 Jun 15
0
[LLVMdev] Question on X86 backend
...that code in my backend, but unless I do the following, the registers are never considered 'live' into the call. / Handle a function call let isCall = 1, Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86,...
2008 Nov 17
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...' ?) def TempRegs : RegisterClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]> { } 3) If not, does this means I have to write the whole LLVM backend based on the basic llvm::TargetMachine & llvm::TargetData, just like what CBackend does? --------------------------------------------------------...
2010 Jun 15
2
[LLVMdev] Question on X86 backend
Hi Micah, > In X86InstrInfo.td for Call Instructions, it mentions that Uses for > argument registers are added manually. Can someone point me to the > location where they are added as the comment doesn't reference a > where or how? the register uses are added by the function X86TargetLowering::LowerCall() during the DAG Lowering phase. This is the relevant code segment: // Add
2011 May 05
1
problem with location of libraries 64-bit (opensuse)
...ally I don`t know rpy2 but maybe someone on this list can decide if the mistake lies on R`s side or on rpy2?s side or in between. R-devel is installed in these cases, I asked. Latest R-base or R-patched is used. The following problem occurs (user report): ----------------------- > Python 2.7 (r27:82500, Aug 07 2010, 16:54:59) [GCC] on linux2 > Type "help", "copyright", "credits" or "license" for more information. > >>> import rpy2.robjects as robjects > Traceback (most recent call last): > File "<stdin>", line...
2008 Sep 08
0
[LLVMdev] Overzealous PromoteCastOfAllocation
...and i32 %A12.ins, -65536 ; <i32> [#uses=1] > %B9.ins = or i32 %V.in8.mask, %B9 ; <i32> [#uses=2] > %R14 = lshr i32 %B9.ins, 16 ; <i32> [#uses=1] > %R15 = trunc i32 %R14 to i16 ; <i16> [#uses=1] > %R27 = trunc i32 %B9.ins to i16 ; <i16> [#uses=1] > call void @bar( i16 %R15, i16 %R27 ) > call void @empty( ) > ret void > } > > However, when I run -deadargelim -die -scalarrepl directly on the > original code, I get the result I expect: > defin...
2008 Nov 20
4
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...ot;, [XXX], 32, [R0, R1, R2, R3,   > > R4, R5, R6, R7, R8, R9, > >                                                    R10, R11, R12,   > > R13, R14, R15, R16, R17, R18, R19, > >                                                    R20, R21, R22,   > > R23, R24, R25, R26, R27, R28, R29, > >                                                    R30, R31]> { > > } > > > 3) If not, does this means I have to write the whole LLVM backend   > > based on the basic llvm::TargetMachine & llvm::TargetData, just like   > > what CBackend does? &...
2008 Nov 18
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...rClass<"MFLEXG", [XXX], 32, [R0, R1, R2, R3, > R4, R5, R6, R7, R8, R9, > R10, R11, R12, > R13, R14, R15, R16, R17, R18, R19, > R20, R21, R22, > R23, R24, R25, R26, R27, R28, R29, > R30, R31]> { > } > > 3) If not, does this means I have to write the whole LLVM backend > based on the basic llvm::TargetMachine & llvm::TargetData, just like > what CBackend does? > > > -----------...
2008 May 28
0
ia64/pv_ops: preparation: move some functions in ivt.S to avoid lack of space.
...- ;; - mov rp=r14 - br.call.sptk.many b6=ia64_handle_irq + /* interrupt handler has become too big to fit this area. */ + br.sptk.many __interrupt END(interrupt) .org ia64_ivt+0x3400 @@ -1125,105 +1086,18 @@ END(account_sys_enter) DBG_FAULT(17) FAULT(17) -ENTRY(non_syscall) - mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER - ;; - SAVE_MIN_WITH_COVER - - // There is no particular reason for this code to be here, other than that - // there happens to be space here that would go unused otherwise. If this - // fault ever gets "unreserved", simply moved the followi...
2008 May 28
0
ia64/pv_ops: preparation: move some functions in ivt.S to avoid lack of space.
...- ;; - mov rp=r14 - br.call.sptk.many b6=ia64_handle_irq + /* interrupt handler has become too big to fit this area. */ + br.sptk.many __interrupt END(interrupt) .org ia64_ivt+0x3400 @@ -1125,105 +1086,18 @@ END(account_sys_enter) DBG_FAULT(17) FAULT(17) -ENTRY(non_syscall) - mov ar.rsc=r27 // restore ar.rsc before SAVE_MIN_WITH_COVER - ;; - SAVE_MIN_WITH_COVER - - // There is no particular reason for this code to be here, other than that - // there happens to be space here that would go unused otherwise. If this - // fault ever gets "unreserved", simply moved the followi...
2008 Jul 17
0
[PATCH 17/29] ia64/pv_ops/xen: define xen paravirtualized instructions for hand written assembly code
...st8.spill [clob0] = r22, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r23, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r24, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r25, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r26, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r27, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r28, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r29, 16; \ + ;; \ +.mem.offset 0, 0; st8.spill [clob0] = r30, 16; \ +.mem.offset 8, 0; st8.spill [clob1] = r31, 16; \ + ;; \ + mov clob1 = ar.unat; \ + movl clob0 = XSI_B1NA...