Displaying 4 results from an estimated 4 matches for "r23r22".
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2012 Jan 27
2
[LLVMdev] Double spills with Greedy regalloc
...code with the backend I'm developing. Probably this issue is for Jakob,
but anyways this is what I'm getting:
STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1)
STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1)
STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1)
STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1)
STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST...
2012 Jan 27
0
[LLVMdev] Double spills with Greedy regalloc
...nd I'm developing. Probably this issue is for Jakob, but anyways this is what I'm getting:
>
> STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1)
> STDWPtrQRr <fi#12>, 0, %R25R24; mem:ST2[FixedStack12](align=1)
> STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
> STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1)
> STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1)
> STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1)
> STDWPtrQRr <fi#15>...
2010 Nov 27
3
[LLVMdev] Register Pairing
...register pairs, split them into the 8bit subregs
perform the addition and combine them again into the pair ready for the next
operation, in this case we're returning the result. This gives me this code
before instr sel:
# Machine code for function foo:
Function Live Ins: %R25R24 in reg%16384, %R23R22 in reg%16385
Function Live Outs: %R25R24
BB#0: derived from LLVM BB %entry
Live Ins: %R25R24 %R23R22
%reg16385<def> = COPY %R23R22; WDREGS:%reg16385 // COPY B
%reg16384<def> = COPY %R25R24; WDREGS:%reg16384 // COPY A
%reg16387<def> = COPY %reg16384:ssub_0; GPR8:...
2010 Nov 29
0
[LLVMdev] Register Pairing
...'t have a number of 16-bit instructions.
[...]
> typedef unsigned short t;
> t foo(t a, t b, t c)
> {
> return a+b;
> }
[...]
> This is fine until we get to the register allocation stage, there it does:
> BB#0: derived from LLVM BB %entry
> Live Ins: %R25R24 %R23R22
> %R18<def> = COPY %R24
> %R19<def> = COPY %R25
> %R24<def> = COPY %R22<kill>, %R25R24<imp-def>
> %R24<def> = ADDRdRr %R24, %R18<kill>, %SREG<imp-def>
> %R25<def> = COPY %R23<kill>
> %R25<def>...