search for: r19r18

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[LLVMdev] Double spills with Greedy regalloc
2012 Jan 27
2
[LLVMdev] Double spills with Greedy regalloc
...t;, 0, %R23R22; mem:ST2[FixedStack13](align=1) STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1) STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1) STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1) STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1) STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1) Each STDWPtrQRr is a spill instruction, but notice that it's spilling everything twice to each frame index. I'm only getting this with the Greedy regalloc, PBQP will not duplicate the s...
[LLVMdev] Double spills with Greedy regalloc
2012 Jan 27
0
[LLVMdev] Double spills with Greedy regalloc
...ST2[FixedStack13](align=1) > STDWPtrQRr <fi#13>, 0, %R23R22; mem:ST2[FixedStack13](align=1) > STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1) > STDWPtrQRr <fi#14>, 0, %R21R20; mem:ST2[FixedStack14](align=1) > STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1) > STDWPtrQRr <fi#15>, 0, %R19R18; mem:ST2[FixedStack15](align=1) > > Each STDWPtrQRr is a spill instruction, but notice that it's spilling everything twice to each frame index. I'm only getting this with the Greedy regalloc, PBQP will not...
[LLVMdev] Possible missed optimization?
2011 Mar 25
2
[LLVMdev] Possible missed optimization?
...%vreg3 RET >From above, the 3rd COPY instruction is redundant since it does exactly the same thing as the second COPY instruction, so the stw (store) instr should take %vreg2 instead of %vreg5. After regalloc we get this code: Live Ins: %R25R24 %R27R26<def> = COPY %R25R24 %R19R18<def> = LDWRd %R27R26<kill>; mem:LD2[%a](align=1)(tbaa=!"int") // <---------- why is R27:R26 killed? %R19R18<def> = ANDIWRdK %R19R18, 255 %R27R26<def> = COPY %R25R24<kill> // <------------------ why is this emitted? STWRr %R27R26<kill>,...