search for: r12d

...si),%r10d /* (NEXT STEP) X[0] */ + add %r11d, %ebx /* dst += ... */ + rol $22, %ebx /* dst <<< s */ + mov %edx, %r11d /* (NEXT STEP) z' = %edx */ + add %ecx, %ebx /* dst += x */ + mov 1*4(%rsi), %r10d /* (NEXT STEP) X[1] */ + mov %edx, %r11d /* (NEXT STEP) z' = %edx */ + mov %edx, %r12d /* (NEXT STEP) z' = %edx */ + not %r11d /* not z */ + lea -165796510(%eax,%r10d),%eax /* Const + dst + ... */ + and %ebx, %r12d /* x & z */ + and %ecx, %r11d /* y & (not z) */ + mov 6*4(%rsi),%r10d /* (NEXT STEP) X[6] */ + or %r11d, %r12d /* (y & (not z)) | (x & z) */ + mov %ecx...

Code: https://godbolt.org/z/T397fo I'm running some performance experiments on a x86-64 linux system, where I've modified LLVM to reserve a register, and I'd like to use that register in my code. Currently, I'm using %r12d, which is callee save, so I don't need to worry about compatibility with existing libraries or system calls. For security reasons, the generated binaries need to be position independent. To access the register, I need to use inline assembly; either for all dependent computations, or just for m...

...%bb.35, %bb.128 succs(1): %bb.37 p3193: phi [+d3194<RBP>(,,u3211):, u3195<RBP>(+d3170,b1526):u1437, u3196<RBP>(d2141,b2486):u2324] p3197: phi [+d3198<RBX>(,,u3216):, u3199<RBX>(+d3138,b1526):u1465, u3200<RBX>(+d3364,b2486):] p3201: phi [+d3202<R12D>(,d1541,):, u3203<R12D>(+d3146,b1526):, u3204<R12D>(d1878,b2486):u3148] p3205: phi [+d3206<#1073741833>(,d1551,u1552):, u3207"<#1073741833>(d1521,b1526):u1524, u3779"<#1073741833>(d1517,b1526):, u3780"<#1073741833>(d1513,b1526):u1522, u3208...

Hi Scott, That #1073741833 is a register mask. They are treated as aggregate registers (essentially sets of registers), so if it includes R9D and R11D, it will be treated as being aliased with both. These separate defs are there because they reach disjoint registers. -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: Scott

https://bugs.freedesktop.org/show_bug.cgi?id=93557 Bug ID: 93557 Summary: Kernel Panic on Linux Kernel 4.4 when loading KDE/KDM on Nvidia GeForce 7025 / nForce 630a Product: xorg Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: blocker

...a simple program I see the following sequence: ADJCALLSTACKDOWN64 0, 0, 0, *implicit-def dead %rsp*, implicit-def dead %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp CALL64pcrel32 @foo, <regmask %bh %bl %bp %bpl %bx %ebp %ebx %rbp %rbx %r12 %r13 %r14 %r15 %r12b %r13b %r14b %r15b %r12d %r13d %r14d %r15d %r12w %r13w %r14w %r15w>, *implicit %rsp*, implicit %ssp, implicit-def %rsp, implicit-def %ssp ADJCALLSTACKUP64 0, 0, implicit-def dead %rsp, implicit-def dead %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp RET 0 The ADJCALLSTACKDOWN64 has implicit-def dead %rs...

...BB0_1 Depth=1 >>>>> # Parent Loop BB0_2 Depth=2 >>>>> # => This Inner Loop >>>>> Header: Depth=3 >>>>> lea r15, [rsi + r14] >>>>> mov r12d, dword ptr [r15 + 4*r11 - 16000] >>>>> imul r12d, dword ptr [rax - 16] >>>>> mov ecx, dword ptr [r15 + 4*r11 - 12000] >>>>> imul ecx, dword ptr [rax - 12] >>>>> mov ebp, dword ptr [r15 + 4*r11 - 8000] >>>>> imul ebp, dword p...

...\ ENTRY(ECX) \ ENTRY(EDX) \ ENTRY(EBX) \ ENTRY(sib) \ ENTRY(EBP) \ ENTRY(ESI) \ ENTRY(EDI) \ ENTRY(R8D) \ ENTRY(R9D) \ ENTRY(R10D) \ ENTRY(R11D) \ ENTRY(R12D) \ ENTRY(R13D) \ ENTRY(R14D) \ ENTRY(R15D) the ENTRY(sib) looks suspicious. that should be ENTRY(ESP), no? thanks. J -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/201309...

...rdi 1a9: 0f 84 e1 00 00 00 je 290 <evo_wait+0x110> 1af: e8 00 00 00 00 callq 1b4 <evo_wait+0x34> 1b4: c1 e8 02 shr $0x2,%eax 1b7: 4c 8d ab 00 01 00 00 lea 0x100(%rbx),%r13 1be: 41 89 c4 mov %eax,%r12d 1c1: 4c 89 ef mov %r13,%rdi 1c4: 45 01 e6 add %r12d,%r14d 1c7: e8 00 00 00 00 callq 1cc <evo_wait+0x4c> 1cc: 41 81 fe f7 03 00 00 cmp $0x3f7,%r14d 1d3: 0f 86 87 00 00 00 jbe 260 <evo_wait+0xe0> 1d...

...loc_100000F0E mov dword ptr [rax+r8*4], 0 xor r11d, r11d loc_100000D84: ; CODE XREF: _main+BA j cmp r15d, 1 mov esi, 0 mov r9, [rsp+48h+var_48] mov r12d, 1 jle short loc_100000DF0 loc_100000D99: ; CODE XREF: _main+15E j mov r10d, [rax+rsi*4] mov ecx, 0FFFFFFFFh mov edi, 1 mov r13, r9 nop word ptr [rax+rax...

...4], 0 >> xor r11d, r11d >> >> loc_100000D84: ; CODE XREF: _main+BA j >> cmp r15d, 1 >> mov esi, 0 >> mov r9, [rsp+48h+var_48] >> mov r12d, 1 >> jle short loc_100000DF0 >> >> loc_100000D99: ; CODE XREF: _main+15E j >> mov r10d, [rax+rsi*4] >> mov ecx, 0FFFFFFFFh >> mov edi, 1 >>...

...d >>>> >>>> loc_100000D84: ; CODE XREF: _main+BA j >>>> cmp r15d, 1 >>>> mov esi, 0 >>>> mov r9, [rsp+48h+var_48] >>>> mov r12d, 1 >>>> jle short loc_100000DF0 >>>> >>>> loc_100000D99: ; CODE XREF: _main+15E j >>>> mov r10d, [rax+rsi*4] >>>> mov ecx, 0FFFFFFFFh >>>>...

...r regmaks collected by RegUsageInfoCollector pass. Function Name : bitrv2 Clobbered Registers: AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI ESP RAX RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B R9B R10B R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W R10W R11W R12W R13W R14W R15W How ever caller of bitrv2, makewt has callee saved registers as per CC, but this code results in segmentation fault when compliled with O1 because makewt has value of *ip in R14 register and that is stored and restore by makewt at begining of ca...

...following sequence: > > ADJCALLSTACKDOWN64 0, 0, 0, *implicit-def dead %rsp*, implicit-def dead > %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp > CALL64pcrel32 @foo, <regmask %bh %bl %bp %bpl %bx %ebp %ebx %rbp %rbx > %r12 %r13 %r14 %r15 %r12b %r13b %r14b %r15b %r12d %r13d %r14d %r15d > %r12w %r13w %r14w %r15w>, *implicit %rsp*, implicit %ssp, implicit-def > %rsp, implicit-def %ssp > ADJCALLSTACKUP64 0, 0, implicit-def dead %rsp, implicit-def dead > %eflags, implicit-def dead %ssp, implicit %rsp, implicit %ssp > RET 0 > > > The A...

...;val" (i.e., storage location rbp - 0x8) is used in the addition to calculate the returned value. However, when I print the RegMask operand for the call machine instruction, I get the following: <regmask %BH %BL %BP %BPL %BX %EBP %EBX %RBP %RBX %R12 %R13 %R14 %R15 %R12B %R13B %R14B %R15B %R12D %R13D %R14D %R15D %R12W %R13W %R14W %R15W> I don't see xmm1 as being preserved across this call. Am I missing something? Thanks for your help! On Wed, Jun 22, 2016 at 5:01 PM, Sanjoy Das <sanjoy at playingwithpointers.com> wrote: > Hi Rob, > > Rob Lyerly via llvm-dev wrot...

...Do a reduction. | 1302 `-----------------------------*/ 1303 yyreduce: 1304 /* yyn is the number of a rule to reduce with. */ 1305 yylen = yyr2[yyn]; 0x0000000000400c14 <rpcalc_parse+628>: mov r15d,r14d 0x0000000000400c17 <rpcalc_parse+631>: movzx r12d,BYTE PTR [r15+0x4015e2] 0x0000000000400c1f <rpcalc_parse+639>: mov eax,0x1 0x0000000000400c24 <rpcalc_parse+644>: mov r13,rax 0x0000000000400c27 <rpcalc_parse+647>: sub r13,r12 0x0000000000400c2a <rpcalc_parse+650>: mov eax,r13...

Hi Xen developers and enthousiasts, Recently I have been having a lot of problems with HVM hosts on a dual Xeon E5606 box. Problem is that HVM hosts don''t work on it at all and crash the server. Today I got the logging to work over an IPMI console so then I compiled a fresh xen-unstable. Apart from the message I posted in the subject the call trace reads as follows: (XEN) Xen call

...ector pass. > > Function Name : bitrv2 > Clobbered Registers: > AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI > ESP RAX > RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B > R9B R10B > R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W > R10W R11W > R12W R13W R14W R15W > > How ever caller of bitrv2, makewt has callee saved registers as per CC, > but this > code results in segmentation fault when compliled with O1 because makewt > has value > of *ip in R14 register and that is stored...

...nction Name : bitrv2 >> Clobbered Registers: >> AH AL AX BH BL BP BPL BX CH CL CX DI DIL EAX EBP EBX ECX EDI EFLAGS ESI >> ESP RAX >> RBP RBX RCX RDI RSI RSP SI SIL SP SPL R8 R9 R10 R11 R12 R13 R14 R15 R8B >> R9B R10B >> R11B R12B R13B R14B R15B R8D R9D R10D R11D R12D R13D R14D R15D R8W R9W >> R10W R11W >> R12W R13W R14W R15W >> >> How ever caller of bitrv2, makewt has callee saved registers as per CC, >> but this >> code results in segmentation fault when compliled with O1 because makewt >> has value >> of *ip in...

I am working on a project where we are integrating an existing pre-RA scheduler into LLVM and we are trying to match our peak register pressure values with the machine instruction schedulers values while using X86. I am finding some mismatches in test cases like the one attached. The registers "AH" and "AL" are live-out but not live-in and I don't see that they are defined