Displaying 20 results from an estimated 1361 matches for "r11".
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2013 Jun 19
2
[LLVMdev] ARM struct byval size > 64 triggers failure
I missed that the testing case is returning a struct.
You are right in VARegSaveSize.
For callee:
sub sp, sp, #16
push {r11, lr}
mov r11, sp
sub sp, sp, #8
str r3, [r11, #20]
str r2, [r11, #16]
str r1, [r11, #12]
ldr r1, [r11, #76]
The beginning of the input struct @ sp_at_entry - 16 - 8 + 12 = sp_at_entry -12
# of leftover bytes 67-12 = 55
r11+76 is @ sp_at_entry - 24 + 76 = sp_at_entry + 52, this is incorrect,...
2007 Dec 02
2
Optimised qmf_synth and iir_mem16
...const spx_coef_t *den,
@ spx_word16_t *y,
@ int N,
@ int ord,
@ spx_mem_t *mem,
@ char *stack)
.global iir_mem16
iir_mem16:
stmdb sp!, { r4-r11, lr }
ldr r5, [sp, #36] @ r0 = x, r1 = den, r2 = y, r3 = N
ldr r4, [sp, #40] @ r4 = mem, r5 = ord
cmp r5, #10
beq .order_10
cmp r5, #8
beq .order_8
ldmia sp!, { r4-r11, pc } @ Mon-supported order, return
@ TODO: try...
2004 Sep 10
1
altivec lpc_restore_signal
...ata_len
mfspr r0,256 ; cache old vrsave
addis r31,0,hi16(0xfffffc00)
ori r31,r31,lo16(0xfffffc00)
mtspr 256,r31 ; declare VRs in vrsave
cmplw cr0,r8,r4 ; i<data_len
bc 4,0,L1400
; load coefficients into v0-v7 and initial history into v8-v15
li r31,0xf
and r31,r8,r31 ; r31: data%4
li r11,16
subf r31,r31,r11 ; r31: 4-(data%4)
slwi r31,r31,3 ; convert to bits for vsro
li r10,-4
stw r31,-4(r9)
lvewx v0,r10,r9
vspltisb v18,-1
vsro v18,v18,v0 ; v18: mask vector
li r31,0x8
lvsl v0,0,r31
vsldoi v0,v0,v0,12
li r31,0xc
lvsl v1,0,r31
vspltisb v2,0
vspltisb v3,-1
vmrglw v2,v2,...
2010 Sep 21
1
[LLVMdev] Possible missed optimization on function calling?
...xtern int msin(int a);
extern int mdiv(int a, int b);
int foo(int a, int b)
{
int a4 = mdiv(mcos(a), msin(b));
return a4;
}
I noticed this while testing it for the backend i'm currently developing,
but it produces exactly the same code for other targets:
march = msp430:
push.w r11
push.w r10
push.w r9
push.w r8
mov.w r14, r11
mov.w r15, r10 ; store a
mov.w r13, r15
mov.w r12, r14 ; pass b
call #msin
mov.w r15, r9
mov.w r14, r8 ; store msin(b)
mov.w r10, r15
mov.w r11, r14 ; pass a
c...
2012 Feb 20
6
[PATCH] arm: restore ELR_hyp and SPSR_hyp on return from hypervisor to hypervisor.
...1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/xen/arch/arm/entry.S b/xen/arch/arm/entry.S
index 0b9cce5..36f1119 100644
--- a/xen/arch/arm/entry.S
+++ b/xen/arch/arm/entry.S
@@ -102,6 +102,10 @@ ENTRY(return_to_guest)
ENTRY(return_to_hypervisor)
ldr lr, [sp, #UREGS_lr]
+ ldr r11, [sp, #UREGS_pc]
+ msr ELR_hyp, r11
+ ldr r11, [sp, #UREGS_cpsr]
+ msr SPSR_hyp, r11
pop {r0-r12}
add sp, #(UREGS_R8_fiq - UREGS_sp); /* SP, LR, SPSR, PC */
eret
--
1.7.2.5
2013 Jun 18
0
[LLVMdev] ARM struct byval size > 64 triggers failure
Hi Rajesh,
The callee code looks okay to me
> Assembly for check114
> ---------------------------------------------------------------
> sub sp, sp, #16
> push {r11, lr}
> mov r11, sp
> sub sp, sp, #8
> str r3, [r11, #20]
> str r2, [r11, #16]
> str r1, [r11, #12]
> ldr r1, [r11, #76]
VARegSaveSize is 16 because we store the first 16 bytes of struct byval in r0 to r3.
Alig...
2013 Jun 18
3
[LLVMdev] ARM struct byval size > 64 triggers failure
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2013 Jun 20
1
[LLVMdev] ARM struct byval size > 64 triggers failure
...ple, on task switches
<-- from web
Manman
On Jun 20, 2013, at 5:35 AM, Rajesh Viswabramana <rajesh.vis at samsung.com> wrote:
>
> Hi All,
>
> I tested earlier with llvm svn 3.3 release source.
> Today I built and tested again with svn trunk, I also got "ldr r1, [r11, #80]", which solves the failure.
> Thanks for all comments.
> It seems similar issue http://llvm.org/bugs/show_bug.cgi?id=15868, fixed already.
>
> I have few queries, Just to get my understandings better. Could you please comment on these,
> - "since ABI says the stack...
2017 Oct 03
2
invalid code generated on Windows x86_64 using skylake-specific features
...elease_50/compiler-rt/lib/builtins/x86_64/chkstk2.S
)
When I replaced it with a simple `ret`, everything worked.
The disassembled ntdll implementation is:
__chkstk:
1800a9f60: 48 83 ec 10 subq $16, %rsp
1800a9f64: 4c 89 14 24 movq %r10, (%rsp)
1800a9f68: 4c 89 5c 24 08 movq %r11, 8(%rsp)
1800a9f6d: 4d 33 db xorq %r11, %r11
1800a9f70: 4c 8d 54 24 18 leaq 24(%rsp), %r10
1800a9f75: 4c 2b d0 subq %rax, %r10
1800a9f78: 4d 0f 42 d3 cmovbq %r11, %r10
1800a9f7c: 65 4c 8b 1c 25 10 00 00 00 movq %gs:16, %r11
1800a9f85: 4d 3b d3 cmpq %r11, %r10
18...
2006 Jun 26
0
[klibc 25/43] ia64 support for klibc
...define ASM_CLOBBERS_4 ASM_CLOBBERS_5, "out4"
+#define ASM_CLOBBERS_5 ASM_CLOBBERS_6, "out5"
+#define ASM_CLOBBERS_6 , "out6", "out7", \
+ /* Non-stacked integer registers, minus r8, r10, r15. */ \
+ "r2", "r3", "r9", "r11", "r12", "r13", "r14", "r16", "r17", "r18", \
+ "r19", "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", \
+ "r28", "r29&...
2014 Feb 08
3
[PATCH 1/2] arm: Use the UAL syntax for ldr<cc>h instructions
On Fri, 7 Feb 2014, Timothy B. Terriberry wrote:
> Martin Storsjo wrote:
>> This is required in order to build using the built-in assembler
>> in clang.
>
> These patches break the gcc build (with "Error: bad instruction").
Ah, right, sorry about that.
> Documentation I've seen is contradictory on which order ({cond}{size} or
> {size}{cond}) is correct.
2012 Mar 02
3
[LLVMdev] Access Violation using ExecutionEngine on 64-bit Windows 8 Consumer Preview
...eems that LLVM inserts 4 calls to the same
function at the start of generated code. The function's disassembly
(taken from nearby computer with Windows 7) is:
00000000773A0DD0 sub rsp,10h
00000000773A0DD4 mov qword ptr [rsp],r10
00000000773A0DD8 mov qword ptr [rsp+8],r11
00000000773A0DDD xor r11,r11
00000000773A0DE0 lea r10,[rsp+18h]
00000000773A0DE5 sub r10,rax
00000000773A0DE8 cmovb r10,r11
00000000773A0DEC mov r11,qword ptr gs:[10h]
00000000773A0DF5 cmp r10,r11
00000000773A0DF8 jae 00000000773A0E10
000...
2015 Sep 11
2
Invalid instruction generated on armV4
...ng to run a rust application on armv4 architecture (arm720tdmi).
Rust is using llvm to generate native code.
Some programs are running well on the target but for more complex applications I receive a Illegal instruction :
gdb disassembling the core dump file gives :
0x401e41dc <+0>: push {r11, lr}
0x401e41e0 <+4>: mov r11, sp
0x401e41e4 <+8>: sub sp, sp, #8
0x401e41e8 <+12>: ldr r0, [r0]
0x401e41ec <+16>: str r0, [sp, #4]
0x401e41f0 <+20>: mov r0, r1
0x401e41f4 <+24>: ldr r1, [sp, #4]
=> 0x401e41f8 <+28>: blx r1
0x401e41f...
2013 Oct 21
1
[LLVMdev] [PATCH] Unwanted r11 in push/pop on Cortex-M.
To recap, this is what I was trying to solve:
This C code:
int bar(int a, int b, int c, int d, int e, int f);
int foo(int a, int b, int c, int d, int e )
{
int x = 3*a;
return bar3(a,b,c,d,e,x);
}
Produced the following assembly output:
foo:
push {r11, lr}
sub sp, #8
bl bar
add sp, #8
pop {r11, pc}
The part I didn't like is that push/pop become 4 bytes instructions because
the register that we picked to "align" the stack pointer does not belong to
the low register set (r0-r7).
After a bit of digging, t...
2012 Oct 02
18
[PATCH 0/3] x86: adjust entry frame generation
This set of patches converts the way frames gets created from
using PUSHes/POPs to using MOVes, thus allowing (in certain
cases) to avoid saving/restoring part of the register set.
While the place where the (small) win from this comes from varies
between CPUs, the net effect is a 1 to 2% reduction on a
combined interruption entry and exit when the full state save
can be avoided.
1: use MOV
2012 Feb 14
0
[LLVMdev] Strange behaviour with x86-64 windows, bad call instruction address
...1C2 int 3
0000000077B3F1C3 int 3
0000000077B3F1C4 int 3
0000000077B3F1C5 int 3
0000000077B3F1C6 nop word ptr [rax+rax]
0000000077B3F1D0 sub rsp,10h
0000000077B3F1D4 mov qword ptr [rsp],r10
0000000077B3F1D8 mov qword ptr [rsp+8],r11
0000000077B3F1DD xor r11,r11
0000000077B3F1E0 lea r10,[rsp+18h]
0000000077B3F1E5 sub r10,rax
0000000077B3F1E8 cmovb r10,r11
0000000077B3F1EC mov r11,qword ptr gs:[10h]
0000000077B3F1F5 cmp r10,r11
0000000077B3F1F8 jae 0000000077B3F210
000...
2012 Nov 01
2
[LLVMdev] Undef registers in dependency graph
Hi,
I see that currently physical register uses marked as "undef" can still
cause dependencies. Is this intentional?
SU(9): %D5<def,undef> = LDrid %R0, 0, %R10<imp-def>, %R11<imp-def>
# preds left : 0
# succs left : 11
# rdefs left : 0
Latency : 1
Depth : 0
Height : 0
Successors:
...
val SU(14): Latency=1
val SU(14): Latency=1
val SU(14): Latency=1
...
SU(14): %D10&l...
2014 Feb 08
0
[PATCH v2] arm: Use the UAL syntax for instructions
...r2, r2, #1 ; j--
; Stall
SMLABB r6, r12, r10, r6 ; sum[0] = MAC16_16(sum[0],x,y_0)
- LDRGTH r14, [r4], #2 ; r14 = *x++
+ LDRHGT r14, [r4], #2 ; r14 = *x++
SMLABT r7, r12, r10, r7 ; sum[1] = MAC16_16(sum[1],x,y_1)
SMLABB r8, r12, r11, r8 ; sum[2] = MAC16_16(sum[2],x,y_2)
SMLABT r9, r12, r11, r9 ; sum[3] = MAC16_16(sum[3],x,y_3)
@@ -319,7 +319,7 @@ xcorr_kernel_edsp_process4_done
SMLABB r7, r14, r11, r7 ; sum[1] = MAC16_16(sum[1],x,y_2)
LDRH r10, [r5], #2 ; r10 = y_4 = *y++
SMLABT...
2018 May 11
2
best way to represent function call with new stack in LLVM IR?
...nal void @cycleEntry(i64, i64) unnamed_addr #2 {
Entry:
call void asm sideeffect " # set the new base pointer for this
function\0A movq %rsi, %rbp\0A # store stack pointer of this function
for later\0A movq %rsp, (%rsi)\0A # save this new stack pointer for use
later\0A movq %rsp, r11\0A # compute the new stack pointer for this
function\0A subq %rdi, %rsi\0A addq %rsp, %rsi \0A movq %rsi,
%rsp\0A # copy args that were passed via the old stack to the new
stack\0A # %r11 marches towards %rdi which is the source
addresses\0A1:\0A cmpq %rdi, %r11\0A je 2\0A movq (...
2017 Oct 20
3
[PATCH v1 06/27] x86/entry/64: Adapt assembly for PIE support
...194,12 +194,15 @@ entry_SYSCALL_64_fastpath:
>> ja 1f /* return -ENOSYS (already in pt_regs->ax) */
>> movq %r10, %rcx
>>
>> + /* Ensures the call is position independent */
>> + leaq sys_call_table(%rip), %r11
>> +
>> /*
>> * This call instruction is handled specially in stub_ptregs_64.
>> * It might end up jumping to the slow path. If it jumps, RAX
>> * and all argument registers are clobbered.
>> */
>> - call *sys_call_...