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...ns Pair64:$b), "FD2S\t$a,$b"),[(set f32:$a, (fpround f64:$b))]>; Example register classes: def Core32: RegisterClass<"XYZ", [i32,f32], 32, (add R0,R1,R2,R3,... def Pair64: RegisterClass<"XYZ", [i64,f64], 64,... (add R0R1, R2R3,... def WideCore : RegisterClass<"XYZ", [i64,f64], 64, (add R0_64, R1_64 ... def R0 : Core<0, "%r0">, DwarfRegNum<[0]>; def R1 : Core<1, "%r1">, DwarfRegNum<[1]>; def R2 : Core<2, "%r2">, DwarfRegNum<[...

Hi, I'm trying to write an LLVM backend for Epiphany arch, and I wonder if someone can give me some advice on how to implement load/store optimization. The CPU itself is 32-bit, but it supports wider 64-bit loads and store. So the basic idea is to make use of those by combining narrow ones. I've checked how it is done in AArch64 and Hexagon, and my current code is very close to the

...MT+02:00) Кому: tstellar at redhat.com Копия: Peter Bel <upcfrost at gmail.com>, LLVM Developers Mailing List <llvm-dev at lists.llvm.org> Тема: Re: [llvm-dev] Wide load/store optimization question One thing you can do is define a register class that is made up of register tuples e.g. r0r1, r2r3, etc., and use that register class for the 64-bit load/store instructions.  This will allow you to do the load/store merging before register allocation without the register constraints. ​Our backend only support load/store for i64 type, hence i64 is not legal for us.I guess Peter's Epip...