search for: r0_r1

Hello, Consider this code (this is all after register allocation): R0<def> = ... R0 // Set lower half (based on the previous value) R1<def> = ... // Set upper half ... = R0_R1 // Use the pair It is my understanding that the use of the whole pair will need to have some sort of a reaching def, i.e. the code will need at least those flags: R0<def> = ... R0 // Set lower half (based on the previous value) R1<def> = ... R0_R1<imp-def> //...

...<def> = ADCrr %R9, %R3<kill>, pred:14, pred:%noreg, opt:%noreg, %CPSR<imp-use,kill> %R0<def> = ANDrr %R3<kill>, %R0<kill>, pred:14, pred:%noreg, opt:%noreg %R1<def> = ORRrr %R0<kill>, %R1<kill>, pred:14, pred:%noreg, opt:%noreg, %R0_R1<imp-def> %R3<def> = ANDri %R7<kill>, 2, pred:14, pred:%noreg, opt:%CPSR<def> %R3<def> = MVNi 0, pred:1, pred:%CPSR<kill>, opt:%noreg %R7<def> = EORrr %R3, %LR<kill>, pred:14, pred:%noreg, opt:%noreg %R7<def> = AND...

Hello everyone, I am trying to write a code to do the following: 1. Get an ARM machine instruction 2. Find destination register of that instruction that has been written 3. set a bit in a vector, according to that register number. (Since it's ARM, I have a 15 bit vector) It means if I have : add r0, r1, r0 I want to get r0 as dest reg and set the index 0 of my vector to 1. I get my machine

...egister banks now, and we even use registers to model some encoding constraints. For example, a few ARM instructions like strexd have two register operands that must be an aligned pair of consecutive GPR registers (like r0, r1). This constraint is modeled with the GPRPair register class containing R0_R1, R2_R3, ... pseudo-registers. Sometimes ISAs also assign assembly names to such pseudo-registers, again from ARM: SPR: (s0, s1, ...) 32-bit floating point registers. DPR: (d0, d1, ...) Even-odd pairs of consecutive S-registers. QPR: (q0, q1, ...) Even-odd pairs of consecutive D-registers. But no...

...ooking for non-implicit > (!isImplicit) defines might be a better approximation. > > Finally, you probably have to be aware of subregisters even for GPRs, > the ARM-mode ldrd instructions can only take sequential pairs, which > LLVM models as a separate register called something like R0_R1. > > > Also I want to know which instructions to excluse from this routine, for > > example str instruction does not write to a dest reg or branch > instruction. > > That's why you should check isDef for the ones you're after. > > Cheers. > > Tim. > --...

...nks now, and we even use registers to model some encoding constraints. > > For example, a few ARM instructions like strexd have two register operands that must be an aligned pair of consecutive GPR registers (like r0, r1). This constraint is modeled with the GPRPair register class containing R0_R1, R2_R3, ... pseudo-registers. > > Sometimes ISAs also assign assembly names to such pseudo-registers, again from ARM: > > SPR: (s0, s1, ...) 32-bit floating point registers. > DPR: (d0, d1, ...) Even-odd pairs of consecutive S-registers. > QPR: (q0, q1, ...) Even-odd pairs of co...