Displaying 1 result from an estimated 1 matches for "r0_r12".
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r0_r1
2013 Jun 25
2
[LLVMdev] Adding a new ARM RegisterClass
...C)> {
let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
let AltOrderSelect = [{
return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
}];
}
However, I'd like the instruction NOT to use the LR. I don't see an existing
RegisterClass defined with R0_R12; something like:
def newGPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12))>;
I can add this new RegisterClass myself and then modify the
pseudo-instruction definition to simply use my new RegisterClass. However,
TableGen creates a set of dynamical...