search for: r0

Displaying 20 results from an estimated 1643 matches for "r0".

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2014 Sep 24
1
[PATCH 1/2] allow path to envyas binary to be specified
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/shader/Makefile | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/shader/Makefile b/src/shader/Makefile index 46658e9..2d789be 100644 --- a/src/shader/Makefile +++ b/src/shader/Makefile @@ -24,20 +24,21 @@ NVF0_SHADERS = xfrm2nvf0.vpc \ videonvf0.fpc SHADERS = $(NVC0_SHADERS)
2017 Jun 27
4
[PATCH v4] nv110/exa: update sched codes
...110.fp b/src/shader/exac8nv110.fp index ce78036..101b67f 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0x0 0x1 t2d 0x8 ipa $r3 a[0x84] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st...
2017 Jul 01
2
[PATCH 1/2] nv110/exa: Remove depbars
...src/shader/videonv110.fpc | 18 ++++++------------ 14 files changed, 36 insertions(+), 69 deletions(-) diff --git a/src/shader/exac8nv110.fp b/src/shader/exac8nv110.fp index ce78036..220d7e5 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -36,12 +36,11 @@ ipa $r3 a[0x84] $r0 0x0 0x1 sched (st 0x0) (st 0x0) (st 0x0) ipa $r2 a[0x80] $r0 0x0 0x1 tex nodep $r0 $r2 0x0 0x0 t2d 0x8 -depbar le 0x5 0x0 0x0 -sched (st 0x0) (st 0x0) (st 0x0) fmul ftz $r3 $r0 $r1 +sched (st 0x0) (st 0x0) (st 0x0) mov $r2 $r3 0xf mov $r1 $r3 0xf -sched (st 0x0) (st 0x0) (st 0x0) mov $r0 $r3...
2017 Jun 10
2
[PATCH v3] nv110/exa: update sched codes
...110.fp b/src/shader/exac8nv110.fp index ce78036..101b67f 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0x0 0x1 t2d 0x8 ipa $r3 a[0x84] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st...
2018 Apr 09
2
How to get the case value from Machine Instruction
...tion. The MI as follows: Frame Objects: fi#0: size=1, align=0, at location [SP] fi#1: size=4, align=4, at location [SP+8] fi#2: size=4, align=4, at location [SP+4] fi#3: size=4, align=4, at location [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8, %cpsr...
2017 Jun 03
2
[PATCH v2] nv110/exa: update sched codes
...110.fp b/src/shader/exac8nv110.fp index ce78036..1c4a4f1 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0x0 0x1 t2d 0x8 ipa $r3 a[0x84] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st...
2017 Jun 07
2
[PATCH v2] nv110/exa: update sched codes
...- a/src/shader/exac8nv110.fp >> +++ b/src/shader/exac8nv110.fp >> @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { >> }; >> #else >> -sched (st 0x0) (st 0x0) (st 0x0) >> +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) >> ipa pass $r0 a[0x7c] 0x0 0x0 0x1 >> mufu rcp $r0 $r0 >> ipa $r3 a[0x94] $r0 0x0 0x1 >> -sched (st 0x0) (st 0x0) (st 0x0) >> +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt >> 0x2) >> ipa $r2 a[0x90] $r0 0x0 0x1 >> tex nodep $r1 $r2 0x0 0x1...
2005 Jan 13
4
load object
Hi, I happen to re-write my codes to save memory and my approach is write my obj into file first and later I load it. However, it seems like: load(filename) can load the object but the function returns the name of the object instead of the reference to it. For example, I have an object called r0.prune, which is saved by save(r0.prune, file='r0.prune') and later, I want to load it by using: load('r0.prune') but I need to put the reference to the object r0.prune into a var or a list. I tried: t<-load('r0.prune'), and class(t) gave me a char, which means t stores t...
2017 Jun 28
1
[PATCH v4] nv110/exa: update sched codes
...er/exac8nv110.fp > > +++ b/src/shader/exac8nv110.fp > > @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { > > }; > > #else > > > > -sched (st 0x0) (st 0x0) (st 0x0) > > +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) > > ipa pass $r0 a[0x7c] 0x0 0x0 0x1 > > mufu rcp $r0 $r0 > > ipa $r3 a[0x94] $r0 0x0 0x1 > > -sched (st 0x0) (st 0x0) (st 0x0) > > +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt > 0x2) > > ipa $r2 a[0x90] $r0 0x0 0x1 > > tex nodep $r1 $r2 0x0 0x1 t...
2018 Apr 10
1
How to get the case value from Machine Instruction
...ps://bugs.llvm.org/show_bug.cgi?id=34902. as follows. ############################# * GCC v7.1 generated assembly ############################# ** Options: -Os -marm -march=armv7-a foo: @ args = 0, pretend = 0, frame = 0 @ frame_needed = 0, uses_anonymous_args = 0 sub r0, r0, #15 push {r4, lr} cmp r0, #5 ldrls pc, [pc, r0, asl #2] b .L1 .L4: .word .L3 .word .L5 .word .L6 .word .L7 .word .L8 .word .L9 .L3: mov r0, #5 bl func .L5:...
2017 Jun 08
1
[PATCH v2] nv110/exa: update sched codes
...v110.fp >> @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { >> }; >> #else >> -sched (st 0x0) (st 0x0) (st 0x0) >> +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt >> 0x1) >> ipa pass $r0 a[0x7c] 0x0 0x0 0x1 >> mufu rcp $r0 $r0 >> ipa $r3 a[0x94] $r0 0x0 0x1 >> -sched (st 0x0) (st 0x0) (st 0x0) >> +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr >> 0x1 wt 0x2) >> ipa $r2 a[0x9...
2017 Jul 01
0
[PATCH v5 2/2] nv110/exa: update sched codes
...110.fp b/src/shader/exac8nv110.fp index 220d7e5..7797ef4 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,22 +25,22 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0xf wr 0x0 wt 0x3) (st 0xf wr 0x0 wt 0x1) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0x0 0x1 t2d 0x8 ipa $r3 a[0x84] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +s...
2018 Apr 09
0
How to get the case value from Machine Instruction
...e MI as follows: Frame Objects: fi#0: size=1, align=0, at location [SP] fi#1: size=4, align=4, at location [SP+8] fi#2: size=4, align=4, at location [SP+4] fi#3: size=4, align=4, at location [SP] Jump Tables: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.0: derived from LLVM BB %0 %r0 = MOVi 0, 14, %noreg, %noreg STRi12 %r0, %stack.1, 14, %noreg %r0 = MOVi 4, 14, %noreg, %noreg STRi12 %r0, %stack.2, 14, %noreg %r0 = LDRi12 %stack.2, 14, %noreg %r0 = SUBri %r0, 1, 14, %noreg, %noreg CMPri %r0, 3, 14, %noreg, implicit-def %cpsr STRi12 %r0, %stack.3, 14, %noreg Bcc %bb.6, 8...
2011 Nov 12
2
[LLVMdev] Thumb-2 code generation error in Apple LLVM at all optimization levels
...factor is meant to be held in floating point register d8. I thought at first it might not be initialized at all, but upon closer examination I think it may actually be initialized from a program counter-relative 32-bit .long constant immediately following my method's code. .loc 1 388 3 ldr r0, [r5] ldr r1, [r4, r0] adds r1, #1 str r1, [r4, r0] .loc 1 390 64 mov r0, r4 ldr r1, [r6] blx _objc_msgSend vmov s0, r0 vmul.f32 d0, d0, d8 vcvt.u32.f32 d0, d0 vmov r0, s0 Ltmp272: .loc 1 392 9 cmp.w r0, #4000 Ltmp273: .loc 1 393 13 it hs blxhs _usleep cmp.w *looks* like a 16-bit c...
2017 Jun 03
0
[PATCH] nv110/exa: update sched codes
...110.fp b/src/shader/exac8nv110.fp index ce78036..1c4a4f1 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0x0 0x1 t2d 0x8 ipa $r3 a[0x84] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st...
2017 Jun 10
0
[PATCH v3] nv110/exa: update sched codes
See the 'wt' on the first fmul in exacanv110.fp, exacmnv110.fp and exasanv110.fp. Any ideas on what could be causing the first fmul to require $r0 and/or $r1? Cheers, Aaryaman On Sat, Jun 10, 2017 at 4:10 PM, Aaryaman Vasishta < jem456.vasishta at gmail.com> wrote: > This patch adds proper delays to maxwell exa shaders. rendercheck tests > seem consistent with/without this patch. I haven't extensively tested > them thoug...
2017 Jun 29
0
[PATCH v4] nv110/exa: update sched codes
...101b67f 100644 > --- a/src/shader/exac8nv110.fp > +++ b/src/shader/exac8nv110.fp > @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { > }; > #else > > -sched (st 0x0) (st 0x0) (st 0x0) > +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) > ipa pass $r0 a[0x7c] 0x0 0x0 0x1 > mufu rcp $r0 $r0 > ipa $r3 a[0x94] $r0 0x0 0x1 > -sched (st 0x0) (st 0x0) (st 0x0) > +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2) > ipa $r2 a[0x90] $r0 0x0 0x1 > tex nodep $r1 $r2 0x0 0x1 t2d 0x8 > ipa $r3 a[0x84] $...
2017 Jun 28
0
[PATCH v4] nv110/exa: update sched codes
...8036..101b67f 100644 > --- a/src/shader/exac8nv110.fp > +++ b/src/shader/exac8nv110.fp > @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { > }; > #else > > -sched (st 0x0) (st 0x0) (st 0x0) > +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) > ipa pass $r0 a[0x7c] 0x0 0x0 0x1 > mufu rcp $r0 $r0 > ipa $r3 a[0x94] $r0 0x0 0x1 > -sched (st 0x0) (st 0x0) (st 0x0) > +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2) > ipa $r2 a[0x90] $r0 0x0 0x1 > tex nodep $r1 $r2 0x0 0x1 t2d 0x8 > ipa $r3 a[0x84] $r0 0x...
2017 Jun 05
0
[PATCH v2] nv110/exa: update sched codes
...1c4a4f1 100644 > --- a/src/shader/exac8nv110.fp > +++ b/src/shader/exac8nv110.fp > @@ -25,23 +25,23 @@ NV110FP_Composite_A8[] = { > }; > #else > > -sched (st 0x0) (st 0x0) (st 0x0) > +sched (st 0xf wr 0x0) (st 0xd wr 0x0 wt 0x1) (st 0xf wr 0x0 wt 0x1) > ipa pass $r0 a[0x7c] 0x0 0x0 0x1 > mufu rcp $r0 $r0 > ipa $r3 a[0x94] $r0 0x0 0x1 > -sched (st 0x0) (st 0x0) (st 0x0) > +sched (st 0xf wr 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x3) (st 0xf wr 0x1 wt 0x2) > ipa $r2 a[0x90] $r0 0x0 0x1 > tex nodep $r1 $r2 0x0 0x1 t2d 0x8 > ipa $r3 a[0x84] $...
2018 Sep 08
0
[PATCH] maxwell,pascal: add scheduling data to shaders
.../src/shader/exac8nv110.fp index ce78036..7537780 100644 --- a/src/shader/exac8nv110.fp +++ b/src/shader/exac8nv110.fp @@ -25,23 +25,24 @@ NV110FP_Composite_A8[] = { }; #else -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x0 wt 0x3f) (st 0xd wr 0x0 wt 0x1) (st 0x1 wr 0x0 wt 0x1) ipa pass $r0 a[0x7c] 0x0 0x0 0x1 mufu rcp $r0 $r0 ipa $r3 a[0x94] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st 0x0) +sched (st 0xf wr 0x1) (st 0x2 wr 0x1 rd 0x0 wt 0x3) (st 0x1 wr 0x0 wt 0x1) ipa $r2 a[0x90] $r0 0x0 0x1 tex nodep $r1 $r2 0x0 0x1 t2d 0x8 ipa $r3 a[0x84] $r0 0x0 0x1 -sched (st 0x0) (st 0x0) (st...