search for: qpx

Hi, everyone, I would like to know if anyone is still making use of the support in the PowerPC backend for the IBM BG/Q supercomputer, including the support for its QPX vector instruction set. If you are, please reply. I'm not aware of any still-running BG/Q machines, and if no one is making use of this functionality, I propose that we remove it. Thanks again, Hal Hal Finkel Lead, Compiler Technology and Programming Languages Leadership Computing Facility Ar...

Hi All, I have faced decoding conflict of DisassemblerTables from TableGen. I have instructions with same encoding and different mnemonic among different architecture versions. I have used Predicates and AssemblerPredicates to distinguish them on Codegen and Assembler but it does not work on Disassembler. When I look at TableGen/FixedLenDecoderEmitter.cpp, once there is decoding conflict,

...d flesh this text out a little to make it easier for users? Eric: do you want to add anything for out-of-tree targets after your TargetMachine changes, etc? I stumbled across http://article.gmane.org/gmane.comp.compilers.llvm.devel/83858, for example Hal: the PowePC notes have a note saying "QPX - Hal, please say a few words" :-) Alex: I think MIR is new for 3.7. Do you want to add something to the notes? Quentin: How far did your shrinkwrap work get in 3.7? If it mostly landed after the branch, maybe add it to the 3.8 (trunk) notes. Alexey: Would you or someone of the OpenMP devel...

I've been working on adding support for a (semi-proprietary) extension for PowerPC called "Paired-Singles". It's a SIMD instruction set supporting various operations on a vector of 2 32-bit floating point numbers. The Extension is found in the PowerPC 750CL, modified variants of it are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and the Nintendo Wii U

...se as part of this project. SLEEF has been used as part of bgclang in this way for several years. The library currently supports several architectures: * x86 - SSE2, FMA4, AVX, AVX2+FMA3 * ARM - NEON (single-precision only) * A pure C (scalar) version * Hal's version supports PowerPC/QPX. It is faily easy to port to other architectures. The library provides similar functionality to Intel's Short Vector Math Library (available with Intel's Compiler). Roadmap: -------- 1) Get agreement on incorporating the library. 2) Renaming the public interface to use only the impl...

...will not be a welcome change. > Thats true, so i guess it depends how many architectures need to do > variable extracts in memory. I have no idea if any architectures we > support are able to do a variable extract in a register, or if all > use memory. At least on PowerPC, when using QPX, we can do this using instructions. > If most use a register, then penalizing the few who do > use memory by inserting a mask seems reasonable. > > > >> > >> The point about speculation at the IR level is interesting. > >> Personally i’m ok with constant i...

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What would be needed in order to make MCJIT work on a new architecture? I am thinking BG/Q and Xeon Phi (native). Let's assume the components required for JIT (core, mcjit, native, etc.) can be cross-compiled and linked with an Intel or IBM compiler for such an architecture, and somehow one manages to execute the application. (I didn't try all that yet.) Also, let's assume there is

.... > > Thats true, so i guess it depends how many architectures need to do > > variable extracts in memory. I have no idea if any architectures we > > support are able to do a variable extract in a register, or if all > > use memory. > > At least on PowerPC, when using QPX, we can do this using > instructions. > > > If most use a register, then penalizing the few who do > > use memory by inserting a mask seems reasonable. > > > > > >> > > >> The point about speculation at the IR level is interesting. > > &gt...

Hi all! It takes the current SLP vectorizer too long to vectorize my scalar code. I am talking here about functions that have a single, huge basic block with O(10^6) instructions. Here's an example: %0 = getelementptr float* %arg1, i32 49 %1 = load float* %0 %2 = getelementptr float* %arg1, i32 4145 %3 = load float* %2 %4 = getelementptr float* %arg2, i32 49 %5 = load

On 22.08.2018 17:52, Ryan Taylor wrote: > This is probably going to effect on other backends and break llvm-lit > for them? Very likely, yes. Can you take a look at how big the fallout is? This might give us a hint about what other frontends might expect, and who needs to be involved in the discussion (if one is needed). Cheers, Nicolai > > On Wed, Aug 22, 2018 at 11:41 AM

Hi Frank, > We are looking at a variety of target architectures. Ultimately we aim to run on BG/Q and Intel Xeon Phi (native). However, running on those architectures with the LLVM technology is planned in some future. As a first step we would target vanilla x86 with SSE/AVX 128/256 as a proof-of-concept. Great! It should be easy to support these targets. When you said wide-vectors I assumed

On Tue, 2012-05-01 at 19:58 -0500, Peter Bergner wrote: > On Tue, 2012-05-01 at 17:47 -0500, Hal Finkel wrote: > > By default it should build for > > whatever the current host is (no special flags required). To > > specifically build for something else, use: > > -ccc-host-triple powerpc64-unknown-linux-gnu > > or > > -ccc-host-triple

----- Original Message ----- > From: "Pete Cooper" <peter_cooper at apple.com> > To: "Paweł Bylica" <chfast at gmail.com> > Cc: "Hal Finkel" <hfinkel at anl.gov>, "LLVMdev" <llvmdev at cs.uiuc.edu> > Sent: Wednesday, July 1, 2015 12:08:37 PM > Subject: Re: [LLVMdev] extractelement causes memory access violation - what

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