search for: qcolombet

...ov 20, 2015, at 6:31 AM, Arnaud A. de Grandmaison <arnaud.degrandmaison at arm.com> wrote: > > +CC llvm-dev > >> -----Original Message----- >> From: Arnaud A. de Grandmaison [mailto:arnaud.degrandmaison at arm.com] >> Sent: 20 November 2015 15:28 >> To: 'qcolombet at apple.com' >> Cc: 'haicheng at codeaurora.org' >> Subject: RE: [llvm-dev] [AArch64] bug in shrink-wrapping >> >> Now with memory leak addressed. >> >> Cheers, >> Arnaud >> >>> -----Original Message----- >>> From: Ar...

...on that uses NewVReg, i.e., you are checking that the class for NewVReg matches the class for NewVReg… which by construction is always true! You want to check "common subclass” of DstRC and SrcRC. Cheers, Q. > > Thanks. > > On Mon, Aug 24, 2015 at 2:09 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > >> On Aug 22, 2015, at 9:10 AM, Ryan Taylor <ryta1203 at gmail.com <mailto:ryta1203 at gmail.com>> wrote: >> >> One last question regarding this please. >> >> Why aren't we simply cha...

...at seems like a better solution?) It's like it's actually picking some reg class first and then trying to fix it's error by adding MORE instructions instead of finding the right reg class the first time. > > Thanks. > > On Wed, Aug 19, 2015 at 1:32 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > >> On Aug 19, 2015, at 9:42 AM, Ryan Taylor <ryta1203 at gmail.com <mailto:ryta1203 at gmail.com>> wrote: >> >> It seems the problem arises from using multiple reg classes for one MI in the td file, I...

AddRegisterOperand calls getVR and yes, I think an IMPLICIT_DEF is being generated. On Tue, Aug 25, 2015 at 2:40 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 11:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I have not tried 3.5, it's a significant amount of work to port from one > version to the next though, I did not personally do the 3.4 to 3.6 porting. > I agree thou...

Hi Quentin, After shrink-wrapping was enabled as default on AArch64, llc has a seg fault when compiling the attached .ll file on AArch64. My command is llc -mcpu=cortex-a57 bug.ll Best, Haicheng -------------- next part -------------- A non-text attachment was scrubbed... Name: bug.ll Type: application/octet-stream Size: 8983 bytes Desc: not available URL:

...his is what I get. This is what I'd like to get: BB#0: derived from LLVM BB %entry %vreg0<def> = MOV16Copy_IMM_REG <ga:@a+1>[TF=1]; PTRRegs:%vreg0 Send_iii %NULLR0, %vreg1<kill>, 1, 1, 1, 1, 0; PTRRegs:%vreg0 RetRA On Tue, Aug 25, 2015 at 3:56 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Oh, could you paste the MIs you get right after ISel (the whole def use > chain of the interesting vregs)? > > Q. > > On Aug 25, 2015, at 12:00 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > AddRegisterOperand calls getVR and yes, I think...

...Base and so the constrainRegClass is failing. > > Using the MI Op's reg class and comparing it directly to the NewVReg class would eliminate this possible issue and should produce more accurate results? > > Thanks. > > On Mon, Aug 24, 2015 at 8:08 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > >> On Aug 24, 2015, at 4:46 PM, Ryan Taylor <ryta1203 at gmail.com <mailto:ryta1203 at gmail.com>> wrote: >> >> Here is the snippet that matters: >> >> void >> InstrEmitter::AddRegi...

...ned even more. Honestly, I really don't understand this part at all, why even have this type checking? If we have defined a RegClass for that instruction, it should use that regclass or subregclasses (depending on use/def info), correct? On Tue, Aug 25, 2015 at 1:37 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 10:29 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > 1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the > multiclass. The IMM in my case is a global. So you can see that > GPRBaseRegs, GPRBaseRegs sets the r...

> On Feb 26, 2019, at 7:25 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > > >> On Feb 26, 2019, at 4:18 PM, Matt Arsenault <arsenm2 at gmail.com <mailto:arsenm2 at gmail.com>> wrote: >> >> >> >>> On Feb 26, 2019, at 7:01 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolo...

Cool test :) It seems to work fine now, I don't see any new failures. IIUC, Kristof is also giving it another run. Cheers, Diana On 30 May 2017 at 22:57, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Diana, > > I’ve actually gone ahead and pushed the fix as I was able to produce a > small reproducer. > > This is r304244 > > Let me know if you encounter any other problem. > > Cheers, > -Quentin > > On May 30, 2017, at 7:42 AM,...

...for the MOV16Copy instruction. I really just want to know if there is any way currently to get the TD defined register class for an operand for a machine instruction. There must be a way since LLVM produces valid registers for the operands. On Tue, Aug 25, 2015 at 1:18 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the instruction in question: > > multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass > srcAReg, > RegisterClass dstReg, Val...

Hi Jonas, I won’t have time to look at it this week after all. I’ll try to do that next week. If you do not hear back from me by end of next, do not hesitate to ping me! Cheers, -Quentin > On Apr 22, 2015, at 9:32 AM, Quentin Colombet <qcolombet at apple.com> wrote: > >> >> On Apr 21, 2015, at 11:49 PM, Jonas Paulsson <jonas.paulsson at ericsson.com <mailto:jonas.paulsson at ericsson.com>> wrote: >> >> I looked at SplitKit, but I am not sure how to best do it, so it would be great if you could t...

...d lead to > unintended spilling? If GPRBaseRegs was used then you could have the base > reg class to choose from instead of spilling. > 2. Ok, yes, that makes sense. > 3. I'll send a second email. > > Thanks. > > On Tue, Aug 25, 2015 at 12:49 PM, Quentin Colombet <qcolombet at apple.com> > wrote: > >> >> On Aug 25, 2015, at 9:36 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: >> >> Quentin, >> >> Yes, this is bound already: >> >> def GPRRegs: RegisterClass<"us", [i32], i32, (add R0,..... RX)...

...} > } > > This does not work. The logic seems sound though, you are checking an RC (DstRC) and the MI's operand's RegClass, get the common sub, which should either be or not be DstRC, right? > > Thanks. > > On Mon, Aug 24, 2015 at 4:44 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > >> On Aug 24, 2015, at 1:30 PM, Ryan Taylor <ryta1203 at gmail.com <mailto:ryta1203 at gmail.com>> wrote: >> >> I'm trying to do something like this: >> >> // Dst = NewVReg's reg...

...d so the constrainRegClass is failing. > > Using the MI Op's reg class and comparing it directly to the NewVReg > class would eliminate this possible issue and should produce more accurate > results? > > Thanks. > > On Mon, Aug 24, 2015 at 8:08 PM, Quentin Colombet <qcolombet at apple.com> > wrote: > >> >> On Aug 24, 2015, at 4:46 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: >> >> Here is the snippet that matters: >> >> void >> InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, >>...

...if I replace the GPR reg class with something different than it picks the base reg class fine, potentially it is using the reg class with most available? idk. I just need to create MIs for every possible case I guess. Thanks for the help! :) On Wed, Aug 19, 2015 at 12:04 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Ryan, > > On Aug 19, 2015, at 6:35 AM, Ryan Taylor via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Essentially it doesn't appear that the reg class assignment is based on > uses and is instead inserting an extra COPY for this. Is...

...the original MI, that seems like a better solution?) It's like it's actually picking some reg class first and then trying to fix it's error by adding MORE instructions instead of finding the right reg class the first time. Thanks. On Wed, Aug 19, 2015 at 1:32 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 19, 2015, at 9:42 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > It seems the problem arises from using multiple reg classes for one MI in > the td file, I guess. > > > Probably, that does not sound something used widely :). >...

Hi Kristof, Thanks for going back so fast! > On May 24, 2017, at 12:57 PM, Kristof Beyls <kristof.beyls at arm.com> wrote: > >> >> On 24 May 2017, at 19:31, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> Hi Kristof, >> >> Thanks for the measurements. >> >>> On May 24, 2017, at 6:00 AM, Kristof Beyls <kristof.beyls at arm.com <mailto:kristof.beyls at arm.com>> wrote: >>>...

Hi Kristof, > On May 25, 2017, at 2:09 AM, Kristof Beyls <kristof.beyls at arm.com> wrote: > >> >> On 24 May 2017, at 22:01, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: >> >> Hi Kristof, >> >> Thanks for going back so fast! >> >>> On May 24, 2017, at 12:57 PM, Kristof Beyls <kristof.beyls at arm.com <mailto:kristof.beyls at arm.com>> wrote: >>&...

...ov] Sent: Monday, January 15, 2018 20:34 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; llvm-dev at lists.llvm.org; Sanjay Patel (spatel at rotateright.com) <spatel at rotateright.com>; Chandler Carruth (chandlerc at gmail.com) <chandlerc at gmail.com>; Quentin Colombet (qcolombet at apple.com) <qcolombet at apple.com>; Craig Topper (craig.topper at gmail.com) <craig.topper at gmail.com> Cc: Breger, Igor <igor.breger at intel.com> Subject: Re: GEP transformation by InstCombiner On 01/15/2018 12:21 PM, Demikhovsky, Elena wrote: Hi all, I'm working on...