search for: colombet

Displaying 20 results from an estimated 532 matches for "colombet".

2016 May 02
2
[RFC] Helping release management
> On May 2, 2016, at 2:48 PM, Joerg Sonnenberger via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On Mon, May 02, 2016 at 02:39:12PM -0700, Quentin Colombet wrote: >> Hi Joerg, >> >>> On May 2, 2016, at 2:33 PM, Joerg Sonnenberger via llvm-dev <llvm-dev at lists.llvm.org> wrote: >>> >>> On Mon, May 02, 2016 at 01:35:27PM -0700, Quentin Colombet via llvm-dev wrote: >>>> 1. Use [Fix] for commit r...
2018 Nov 28
4
[RFC] Tablegen-erated GlobalISel Combine Rules
Le mer. 28 nov. 2018 à 11:41, David Greene <dag at cray.com> a écrit : > > Quentin Colombet <quentin.colombet at gmail.com> writes: > > > And are there any realistic alternatives for declarative > > representations combines? > > > > Realistic I would have thought we can use the syntax we already have > > for SDISel. > > In other words,...
2015 Apr 24
2
[LLVMdev] Multiple connected components in live interval
Hi Jonas, I won’t have time to look at it this week after all. I’ll try to do that next week. If you do not hear back from me by end of next, do not hesitate to ping me! Cheers, -Quentin > On Apr 22, 2015, at 9:32 AM, Quentin Colombet <qcolombet at apple.com> wrote: > >> >> On Apr 21, 2015, at 11:49 PM, Jonas Paulsson <jonas.paulsson at ericsson.com <mailto:jonas.paulsson at ericsson.com>> wrote: >> >> I looked at SplitKit, but I am not sure how to best do it, so it would be great...
2018 Aug 06
2
Getting Object Files During LTO
On Mon, Aug 6, 2018 at 4:30 PM Quentin Colombet <quentin.colombet at gmail.com> wrote: > Hi Bill, > > > 2018-08-06 16:13 GMT-07:00 Bill Wendling via llvm-dev < > llvm-dev at lists.llvm.org>: > > Is there a way to get object files from the LTO step before the linker > > performs the final link phase? What I...
2017 May 30
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
...e that helps, > Diana > > > On 29 May 2017 at 10:06, Diana Picus <diana.picus at linaro.org> wrote: >> Thanks Quentin, it's in progress now, I'll let you know how it goes. >> >> Cheers, >> Diana >> >> On 27 May 2017 at 03:36, Quentin Colombet <qcolombet at apple.com> wrote: >>> Hi Kristof, >>> >>> I’ve pushed the localizer in r304051 and added it in the AArch64 O0 pipeline >>> in r304052. >>> >>> I let Diana investigate the seg fault she was seeing. >>> >>>...
2017 May 31
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Cool test :) It seems to work fine now, I don't see any new failures. IIUC, Kristof is also giving it another run. Cheers, Diana On 30 May 2017 at 22:57, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Diana, > > I’ve actually gone ahead and pushed the fix as I was able to produce a > small reproducer. > > This is r304244 > > Let me know if you encounter any other problem. > > Cheers, > -Quentin > > On May 30, 2017...
2019 Nov 20
2
imm COPY generated by PHI elim not propagated
I was looking at writing a pass after PHI elim to do this, just trying to dump the reaching def MIs but get lots of no live segments issues. Have included addREquired and addPreserved for LiveIntervals and setPreservesAll(). -Ryan On Fri, Nov 15, 2019 at 2:58 PM Quentin Colombet <qcolombet at apple.com> wrote: > You could do it after RA and before rewrite, when you still have the live > intervals around. > > On Nov 15, 2019, at 11:16 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > This would require getting the reaching definition which re...
2016 Nov 18
5
LoopStrengthReduce Code Owner: nominating Quentin
I’d like to nominate Quentin Colombet as LSR code owner. He has handled most of the reviews for me for the past couple years (thanks Quentin), and is willing to take on the responsiblity. Frankly, turning over ownership to Quentin is overdue. -Andy
2014 Sep 05
5
[LLVMdev] [PATCH] [MachineSinking] Conservatively clear kill flags after coalescing.
...t simply transfer the value of the kill flag from the SrcReg to the DstReg. We are extending the live-range of SrcReg. I do not see how you could relate that to the kill flag of DstReg. Therefore, I still think, this is the right fix. -Quentin > > -Juergen > > On 09/05/14, Quentin Colombet <qcolombet at apple.com> wrote: >> >> Hi Patrik, >> >> >> LGTM. >> >> Thanks, >> -Quentin >> On Sep 5, 2014, at 1:03 AM, Patrik Hägglund H <patrik.h.hagglund at ericsson.com> wrote: >> >>> Hi Quentin, >>>...
2017 May 29
2
[GlobalISel][AArch64] Toward flipping the switch for O0: Please give it a try!
Thanks Quentin, it's in progress now, I'll let you know how it goes. Cheers, Diana On 27 May 2017 at 03:36, Quentin Colombet <qcolombet at apple.com> wrote: > Hi Kristof, > > I’ve pushed the localizer in r304051 and added it in the AArch64 O0 pipeline > in r304052. > > I let Diana investigate the seg fault she was seeing. > > @Diana, let me know if you need help. > > Cheers, > -Quen...
2017 Jan 27
3
RFC: Building GlobalISel by default
On 27 January 2017 at 00:12, Quentin Colombet <qcolombet at apple.com> wrote: > Thanks all the feedbacks. > > I moved forward, the switch happened in r293232. Thanks! > For incremental buildbots, I believe we are going to need to kick a clean > build for them to pick it up. > @Galina, is it something you can do? Unf...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
AddRegisterOperand calls getVR and yes, I think an IMPLICIT_DEF is being generated. On Tue, Aug 25, 2015 at 2:40 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 11:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I have not tried 3.5, it's a significant amount of work to port from one > version to the next though, I did not personally do the 3.4 to 3.6 porting. &gt...
2015 May 27
6
[LLVMdev] [Shrink-Wrapping] Request For Benchmarking: X86 and AArch64
Hi, Shrink-wrapping capabilities, i.e., better placement of prologue and epilogue sequences, landed in r236507 but are not yet enabled by default. Since r236507 AArch64 is shrink-wrapping ready, meaning we can turn the pass on for this target. I’ve done the same for X86 in r 238293. Now, I need your help to test and benchmark how shrink-wrapping perform on those targets. The goal is to decide
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...g1 RetRA This is what I get. This is what I'd like to get: BB#0: derived from LLVM BB %entry %vreg0<def> = MOV16Copy_IMM_REG <ga:@a+1>[TF=1]; PTRRegs:%vreg0 Send_iii %NULLR0, %vreg1<kill>, 1, 1, 1, 1, 0; PTRRegs:%vreg0 RetRA On Tue, Aug 25, 2015 at 3:56 PM, Quentin Colombet <qcolombet at apple.com> wrote: > Oh, could you paste the MIs you get right after ISel (the whole def use > chain of the interesting vregs)? > > Q. > > On Aug 25, 2015, at 12:00 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > AddRegisterOperand calls getVR an...
2016 May 02
2
[RFC] Helping release management
Hi Joerg, > On May 2, 2016, at 2:33 PM, Joerg Sonnenberger via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On Mon, May 02, 2016 at 01:35:27PM -0700, Quentin Colombet via llvm-dev wrote: >> 1. Use [Fix] for commit related to bug fixes. > > I'm not really such a big fan of this format, adds too much noise. What alternatives do you have in mind? > >> 2. Add a description of the problem in the commit message to help answer the followin...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...gets constrained even more. Honestly, I really don't understand this part at all, why even have this type checking? If we have defined a RegClass for that instruction, it should use that regclass or subregclasses (depending on use/def info), correct? On Tue, Aug 25, 2015 at 1:37 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 10:29 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > 1. MOV16Copy_IMM_REG is the instruction matched, sorry. AD is the > multiclass. The IMM in my case is a global. So you can see that > GPRBaseRegs, GPRBaseR...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...hence GPR != Base and so the constrainRegClass is failing. > > Using the MI Op's reg class and comparing it directly to the NewVReg class would eliminate this possible issue and should produce more accurate results? > > Thanks. > > On Mon, Aug 24, 2015 at 8:08 PM, Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > >> On Aug 24, 2015, at 4:46 PM, Ryan Taylor <ryta1203 at gmail.com <mailto:ryta1203 at gmail.com>> wrote: >> >> Here is the snippet that matters: >> >> void >> InstrEm...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...ectly allowed for the MOV16Copy instruction. I really just want to know if there is any way currently to get the TD defined register class for an operand for a machine instruction. There must be a way since LLVM produces valid registers for the operands. On Tue, Aug 25, 2015 at 1:18 PM, Quentin Colombet <qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the instruction in question: > > multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass > srcAReg, > RegisterCla...
2013 Jul 26
3
[LLVMdev] [RFC] Add warning capabilities in LLVM.
On 07/25/2013 05:09 PM, Quentin Colombet wrote: > Hi, > > I think we have a consensus on how we should report diagnostics now. > For broader uses, the discussion is still open. > > To move forward on the diagnostic part, here is the plan: > - Extend the current handler with a prototype like: > void report(enum Kind...
2015 Dec 04
2
analyzePhysReg question
> On Dec 3, 2015, at 5:36 PM, Quentin Colombet via llvm-dev <llvm-dev at lists.llvm.org> wrote: > >> >> On Dec 3, 2015, at 5:11 PM, Smith, Kevin B <kevin.b.smith at intel.com <mailto:kevin.b.smith at intel.com>> wrote: >> >> >> >>> -----Original Message----- >>> From: Que...