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Few comments below. On 10/16/2016 09:14 PM, Ilia Mirkin wrote: > This flips GM10x to using the updated format, which is what I tested > with. However GM20x and GP10x also use this TIC format. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nvc0_accel.c | 11 ++++++++++ > src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++ >

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Would be nice if someone could glance at this... I suppose I could also compare object files. Yeah, I should probably do that. src/nv10_exa.c | 8 ++++---- src/nv30_exa.c | 20 ++++++++++---------- src/nv40_exa.c | 8 ++++---- src/nv50_accel.c | 6 +++--- src/nv50_accel.h | 1 + src/nv50_exa.c

Are you sure this refactoring doesn't break anything? Few comments inline. On 10/27/2016 04:02 PM, Ilia Mirkin wrote: > This flips GM10x to using the updated format, which is what I tested > with. However GM20x and GP10x also use this TIC format. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- > src/nvc0_accel.c | 11 ++++++++++ > src/nvc0_accel.h |

This flips GM10x to using the updated format, which is what I tested with. However GM20x and GP10x also use this TIC format. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/nvc0_accel.c | 11 ++++++++++ src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++ src/nvc0_exa.c | 22 ++++--------------- src/nvc0_xv.c | 67

This flips GM10x to using the updated format, which is what I tested with. However GM20x and GP10x also use this TIC format. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/nvc0_accel.c | 11 ++++++++++ src/nvc0_accel.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++ src/nvc0_exa.c | 23 ++++--------------- src/nvc0_xv.c | 67

On Mon, Oct 17, 2016 at 5:46 AM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > Few comments below. > > On 10/16/2016 09:14 PM, Ilia Mirkin wrote: >> >> This flips GM10x to using the updated format, which is what I tested >> with. However GM20x and GP10x also use this TIC format. >> >> Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>

We still have to push everything out, might as well kick earlier and flip pushbufs when we know we'll need it. This resolves some issues with the new policy of making sure that we always leave a bit of room at the end for fences. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: mesa-stable at lists.freedesktop.org --- src/gallium/drivers/nouveau/nv50/nv50_shader_state.c | 9

Unfortunately there's only one RT_ARRAY_MODE setting for all attachments, so clears were previously truncated to the minimum number of layers any attachment had. Instead set the RT_ARRAY_MODE to 512 (the max number of layers) before doing the clear. This fixes gl-3.2-layered-rendering-clear-color-mismatched-layer-count. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> ---

This patch-series implements the ARB_viewport_array for nvc0 and does a little house-cleanig afterwords. Tobias Klausmann (3): nvc0: implement multiple viewports/scissors, enable ARB_viewport_array nvc0: mark scissor in nvc0_clear_{} nv50/ir: Remove NV50_SEMANTIC_VIEWPORTINDEX and its last consumer .../drivers/nouveau/codegen/nv50_ir_driver.h | 1 -

Hi, please review the following patch! Thanks, Tobias Klausmann

v2: - change patch name to "nvc0: implement clear_buffer" - rename nvc0_clear_buffer_rgb32 -> nvc0_clear_buffer_cpu and make it work for all formats - remove superfluous fenciing in nvc0_clear_buffer_cpu - coding style fixes v3: - more coding style fixes - nvc0_clear_buffer() - don't mark the framebuffer dirty for if we don't touch the GPU Signed-off-by: Tobias

Commit 1dce6264045cd23e9c07574ed0bb31c7dce9354f introduced a regression spotted on several G94 (FDObz #85160). This device seems to expect the vblank period to be set after setting scale instead of before. V2: shove this in a separate function This is a candidate bug-fix for 3.18 Signed-off-by: Roy Spliet <rspliet at eclipso.eu> Tested-by: Zlatko Calusic <zcalusic at bitsync.net>

This patch-series implements the ARB_viewport_array for nvc0 and does a little house-cleanig afterwords. V2: Add Release-Notes, mark this in GL3 as done for nvc0 Don't mark the scissors dirty when we don't need to do that Tobias Klausmann (3): nvc0: implement multiple viewports/scissors, enable ARB_viewport_array docs: update GL3.txt, relnotes: mark GL_ARB_viewport_array as done

v2: change patch according to Ilia Mirkins review --- src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 151 ++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c index 6b7c30c..242924a 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c +++

I am getting the following build break on changeset 13662. I am compiling on x86_64 SLES10 with gcc 4.1.0. Is there a fix for this? Thanks, Aravindh Puthiyaparambil Xen Development Team Unisys, Tredyffrin PA make[1]: Entering directory `/root/xen/xen-unstable.hg/tools/firmware'' make[2]: Entering directory `/root/xen/xen-unstable.hg/tools/firmware/rombios'' gcc -o biossums

Fixes fbo-drawbuffers-none glClearBuffer piglit test. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- Only tested on nv50, but implementations seem similar enough. src/gallium/drivers/nouveau/nv50/nv50_surface.c | 17 +++++++++-------- src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 17 +++++++++-------- 2 files changed, 18 insertions(+), 16 deletions(-) diff --git

On Sat, Oct 10, 2015 at 3:41 PM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > This patch looks fine except that it should be a bit more normalized. I > mean, sometimes you break when PUSH_SPACE fails, sometimes not. Same for > PUSH_SPACE calls, sometimes you add it sometimes not. Meh. We need to get our error checking situation straight, but this isn't the patch to

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de> --- src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 7 +- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 20 ++-- src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 3 + src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 27 ++++-

On Thu, Oct 27, 2016 at 1:19 PM, Samuel Pitoiset <samuel.pitoiset at gmail.com> wrote: > Are you sure this refactoring doesn't break anything? > > Few comments inline. > > > On 10/27/2016 04:02 PM, Ilia Mirkin wrote: >> >> This flips GM10x to using the updated format, which is what I tested >> with. However GM20x and GP10x also use this TIC format.

On Fri, Oct 31, 2014 at 8:00 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > On Thu, Oct 30, 2014 at 5:57 PM, Roy Spliet <rspliet at eclipso.eu> wrote: >> Commit 1dce6264045cd23e9c07574ed0bb31c7dce9354f introduced a regression spotted >> on several G94 (FDObz #85160). This device seems to expect the vblank period to > > I believe that's often done as a >