search for: pushbuf_base

...b/drivers/gpu/drm/nouveau/nouveau_dma.c index e1a0adb..8930420 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.c +++ b/drivers/gpu/drm/nouveau/nouveau_dma.c @@ -113,8 +113,13 @@ READ_GET(struct nouveau_channel *chan, uint32_t *get) val = nvchan_rd32(chan->user_get); if (val < chan->pushbuf_base || - val >= chan->pushbuf_base + chan->pushbuf_bo->bo.mem.size) + val >= chan->pushbuf_base + chan->pushbuf_bo->bo.mem.size) { + /* meaningless to dma_wait() except to know whether the + * GPU has stalled or not + */ + *get = val; return false; + } *get...

Use ioremap() for mapping the channel user regs (that are never exposed to user space) instead of drm_addmap(). This removes the last use cases of drm_addmap/drm_rmmap from Nouveau. Signed-off-by: Pekka Paalanen <pq at iki.fi> --- drivers/gpu/drm/nouveau/nouveau_channel.c | 13 ++++++------- drivers/gpu/drm/nouveau/nouveau_drv.h | 9 +++------

...ma.c @@ -115,14 +115,43 @@ READ_GET(struct nouveau_channel *chan, uint32_t *get) return true; } +static int +dma_wait_ring_wrap(struct nouveau_channel *chan, int size, uint32_t get, + int *timeout) +{ + /* Emit jump to the start of the ring buffer. */ + OUT_RING(chan, 0x20000000 | chan->pushbuf_base); + + if (get <= NOUVEAU_DMA_SKIPS) { + /* corner case - will be idle */ + if (chan->dma.put <= NOUVEAU_DMA_SKIPS) + WRITE_PUT(NOUVEAU_DMA_SKIPS + 1); + + for (; *timeout; (*timeout)--) { + if (READ_GET(chan, &get) && get > NOUVEAU_DMA_SKIPS) + break; + + DRM_UDE...

...->id), ~0, @@ -127,6 +128,8 @@ nv04_fifo_create_context(struct nouveau_channel *chan) if (ret) return ret; + spin_lock_irqsave(&dev_priv->context_switch_lock, flags); + /* Setup initial state */ dev_priv->engine.instmem.prepare_access(dev, true); RAMFC_WR(DMA_PUT, chan->pushbuf_base); @@ -144,6 +147,8 @@ nv04_fifo_create_context(struct nouveau_channel *chan) /* enable the fifo dma operation */ nv_wr32(dev, NV04_PFIFO_MODE, nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id)); + + spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); return 0; }...

Introduce accessors for TTM buffer object memory that has been mapped into the kernel virtual address space or as IO memory. IO memory needs to be accessed via special accessor functions, not by dereferencing the iomem cookie. The wrappers hide the details of 32-bit access and honour the TTM map type. nv04_crtc_cursor_set() is changed to use the new wrappers. 'cursor' is received from

...rs/gpu/drm/nouveau/nouveau_dma.h @@ -128,6 +128,14 @@ FIRE_RING(struct nouveau_channel *chan) } static inline void +RING_WAIT(struct nouveau_channel *chan) +{ + nouveau_wait_until(chan->dev, 2000000000ULL, + NV50_PDISPLAY_USER_GET(0), 0xffffffff, + (chan->dma.cur << 2) + chan->pushbuf_base); +} + +static inline void WIND_RING(struct nouveau_channel *chan) { chan->dma.cur = chan->dma.put; diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c index d8e8f1b..dba8b93 100644 --- a/drivers/gpu/drm/nouveau/nv50_crtc.c +++ b/drivers/gpu/drm/nouveau/...

Revised patch set v2. [PATCH 1/8] drm/nouveau: bo read/write wrappers for nv04_crtc.c [PATCH 2/8] drm/nouveau: use bo accessors for push buffers [PATCH 3/8] drm/nouveau: OUT_RINGp - optimize OUT_RING loops [PATCH 4/8] drm/nv50: proper notifier_bo access in nv50_display_vblank_crtc_handler() [PATCH 5/8] drm/nouveau: access fbcon notifier via bo accessors [PATCH 6/8] drm/nouveau: screen_base and