Displaying 20 results from an estimated 43 matches for "push_datah".
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2014 Sep 01
2
[PATCH 1/3] nv50: set the miptree address when clearing bo's in vp2 init
The mt address is about to be used more, make sure it's set
appropriately.
Reported-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Emil Velikov <emil.l.velikov at gmail.com>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.2 10.3" <mesa-stable at lists.freedesktop.org>
---
src/gallium/drivers/nouveau/nv50/nv84_video.c | 2 ++
1 file
2015 Oct 10
3
[PATCH] nv50, nvc0: don't base decisions on available pushbuf space
...- unsigned nr;
-
- nr = PUSH_AVAIL(push);
- nr = MIN2(nr - 7, words);
- nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN - 1);
+ unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
+ PUSH_SPACE(push, nr + 7);
BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
PUSH_DATAh(push, bo->offset + base);
PUSH_DATA (push, bo->offset + base);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
index aaec60a..d459dd6 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
+++ b/src/gallium/drivers...
2015 Oct 10
2
[PATCH] nv50, nvc0: don't base decisions on available pushbuf space
...;> - nr = MIN2(nr - 7, words);
>> - nr = MIN2(nr, NV04_PFIFO_MAX_PACKET_LEN - 1);
>> + unsigned nr = MIN2(words, NV04_PFIFO_MAX_PACKET_LEN);
>> + PUSH_SPACE(push, nr + 7);
>> BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
>> PUSH_DATAh(push, bo->offset + base);
>> PUSH_DATA (push, bo->offset + base);
>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
>> b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
>> index aaec60a..d459dd6 100644
>> --- a/src/gallium/drivers/nouveau/...
2014 May 27
1
[PATCH V3] nvc0: implement clear_buffer
...push, color.f[2]);
+ PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, width << 16);
+ PUSH_DATA (push, height << 16);
+
+ IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1);
+
+ BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
+ PUSH_DATAh(push, buf->address + offset);
+ PUSH_DATA (push, buf->address + offset);
+
+ PUSH_DATA (push, width * data_size);
+ PUSH_DATA (push, height);
+
+ PUSH_DATA (push, nvc0_format_table[dst_fmt].rt);
+ PUSH_DATA (push, 1 << 12);
+ PUSH_DATA (push, 1);
+ PUSH_DATA (push, 0);
+...
2014 May 26
1
[PATCH V2] nvc0: implement clear_buffer
...PUSH_DATAf(push, color.f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, width << 16);
+ PUSH_DATA (push, height << 16);
+
+ IMMED_NVC0(push, NVC0_3D(RT_CONTROL), 1);
+
+ BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
+ PUSH_DATAh(push, buf->address + offset);
+ PUSH_DATA (push, buf->address + offset);
+
+ PUSH_DATA (push, width * data_size);
+ PUSH_DATA (push, height);
+
+ PUSH_DATA (push, nvc0_format_table[dst_fmt].rt);
+ PUSH_DATA (push, 1 << 12);
+ PUSH_DATA (push, 1);
+ PUS...
2014 May 26
2
Implement buffer_clear for nvc0
Hi, please review the following patch!
Thanks,
Tobias Klausmann
2014 May 26
0
[PATCH] nvc0: Implement buffer_clear for this type of hardware
...f[3]);
+ BEGIN_NVC0(push, NVC0_3D(SCREEN_SCISSOR_HORIZ), 2);
+ PUSH_DATA (push, width << 16);
+ PUSH_DATA (push, height << 16);
+
+ BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
+ PUSH_DATA (push, 1);
+
+ BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(0)), 9);
+ PUSH_DATAh(push, buf->address + offset);
+ PUSH_DATA (push, buf->address + offset);
+
+ PUSH_DATA (push, width * data_size);
+ PUSH_DATA (push, height);
+
+ PUSH_DATA (push, nvc0_format_table[dst_fmt].rt);
+ PUSH_DATA (push, 1 << 12);
+ PUSH_DATA (push, 1);
+ PUS...
2014 Oct 21
0
[PATCH v2] nv50: Handle ARB_conditional_render_inverted and enable it
...ode == PIPE_RENDER_COND_BY_REGION_WAIT) {
+ if (wait) {
BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1);
PUSH_DATA (push, 0);
}
+ PUSH_SPACE(push, 8);
+ PUSH_REFN (push, q->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
BEGIN_NV04(push, NV50_3D(COND_ADDRESS_HIGH), 3);
PUSH_DATAh(push, q->bo->offset + q->offset);
PUSH_DATA (push, q->bo->offset + q->offset);
- PUSH_DATA (push, NV50_3D_COND_MODE_RES_NON_ZERO);
+ PUSH_DATA (push, cond);
BEGIN_NV04(push, NV50_2D(COND_ADDRESS_HIGH), 2);
PUSH_DATAh(push, q->bo->offset + q->offset);
dif...
2016 Feb 15
2
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...vc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index d435bec..820e38d 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev)
> PUSH_DATAh(push, screen->txc->offset);
> PUSH_DATA (push, screen->txc->offset);
> PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
> + if (screen->eng3d->oclass >= GM107_3D_CLASS) {
> + screen->tic.maxwell = true;
> + if (screen->eng3d->oclass == GM1...
2014 May 21
2
[Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
...TA (push, (height << 16) | dsty);
> + BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
> + PUSH_DATA (push, 8192 << 16);
> + PUSH_DATA (push, 8192 << 16);
> + nv50->scissors_dirty |= 1;
> +
> BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
> PUSH_DATAh(push, bo->offset + sf->offset);
> PUSH_DATA (push, bo->offset + sf->offset);
> @@ -390,7 +406,7 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
> (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
> }
>
> - nv50->dirty |= NV50_NEW...
2016 Oct 17
1
[PATCH] exa: add GM10x acceleration support
...urn;
>>
>> + if (pNv->dev->chipset >= 0x110) {
>> + BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
>> + PUSH_DATA (push, 256);
>> + PUSH_DATA (push, (pNv->scratch->offset + PVP_DATA) >> 32);
>
>
> No PUSH_DATAh in the DDX?
Nope. Didn't feel the burning need to add a helper either.
>> $(filter %nvc0.vpc,$(SHADERS)): %.vpc: %.vp
>> - cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m nvc0 -o $@
>> + cpp -DENVYAS $< | sed -e '/^#/d' | $(ENVYAS) -w -m...
2014 Jan 15
3
[PATCH] nv50, nvc0: don't crash on a null cbuf
.../* Do we need to clear the old RT settings? */
+ if (!fb->cbufs[i])
+ continue;
+
+ sf = nv50_surface(fb->cbufs[i]);
+ res = nv04_resource(sf->base.texture);
+ bo = res->bo;
BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
PUSH_DATAh(push, res->address + sf->offset);
--
1.8.3.2
2016 Feb 15
0
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index d435bec..820e38d 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev)
PUSH_DATAh(push, screen->txc->offset);
PUSH_DATA (push, screen->txc->offset);
PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
+ if (screen->eng3d->oclass >= GM107_3D_CLASS) {
+ screen->tic.maxwell = true;
+ if (screen->eng3d->oclass == GM107_3D_CLASS) {
+...
2016 Feb 15
0
[PATCH 23/23] nvc0: implement support for maxwell texture headers
...src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> index d435bec..820e38d 100644
>> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> @@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev)
>> PUSH_DATAh(push, screen->txc->offset);
>> PUSH_DATA (push, screen->txc->offset);
>> PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
>> + if (screen->eng3d->oclass >= GM107_3D_CLASS) {
>> + screen->tic.maxwell = true;
>> + if (screen->eng...
2014 Jun 17
0
[PATCH try 2 2/2] gallium/nouveau: move pushbuf and fences to context
...ruct nouveau_pushbuf *push;
+
+ nv50 = container_of(mgr, nv50, base.fence);
+ push = nv50->base.pushbuf;
+
+ /* we need to do it after possible flush in MARK_RING */
+ *sequence = ++nv50->base.fence.sequence;
+
+ PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
+ PUSH_DATAh(push, nv50->fence.bo->offset + nv50->fence.ofs);
+ PUSH_DATA (push, nv50->fence.bo->offset + nv50->fence.ofs);
+ PUSH_DATA (push, *sequence);
+ PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
+ NV50_3D_QUERY_GET_UNK4 |
+ NV50_3D_QUE...
2013 Jun 30
0
[PATCH v2] nv50: H.264/MPEG2 decoding support via VP2, available on NV84-NV96, NVA0
...H_REFN(screen->pushbuf, dec->fence, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
+ /* The clear_render_target is done via 3D engine, so use it to write to a
+ * sempahore to indicate that it's done.
+ */
+ BEGIN_NV04(screen->pushbuf, NV50_3D(QUERY_ADDRESS_HIGH), 4);
+ PUSH_DATAh(screen->pushbuf, dec->fence->offset);
+ PUSH_DATA (screen->pushbuf, dec->fence->offset);
+ PUSH_DATA (screen->pushbuf, 1);
+ PUSH_DATA (screen->pushbuf, 0xf010);
+ PUSH_KICK (screen->pushbuf);
+
+ PUSH_SPACE(bsp_push, 2 + 12 + 2 + 4 + 3);
+
+...
2014 Jun 17
2
[PATCH try 2 1/2] gallium/nouveau: decouple nouveau_fence implementation from screen
Signed-off-by: Maarten Lankhorst <maarten.lankhorst at canonical.com>
---
src/gallium/drivers/nouveau/nouveau_fence.c | 76 ++++++++++++-------------
src/gallium/drivers/nouveau/nouveau_fence.h | 22 +++++--
src/gallium/drivers/nouveau/nouveau_screen.c | 9 +++
src/gallium/drivers/nouveau/nouveau_screen.h | 14 ++---
src/gallium/drivers/nouveau/nv30/nv30_context.c | 4 +-
2013 Jun 27
4
[PATCH] nv50: H.264/MPEG2 decoding support via VP2, available on NV84-NV96, NVA0
...ref[0].bo = dec->fence;
+ nouveau_pushbuf_refn(screen->pushbuf, fence_ref, 1);
+ /* The clear_render_target is done via 3D engine, so use it to write to a
+ * sempahore to indicate that it's done.
+ */
+ BEGIN_NV04(screen->pushbuf, SUBC_3D(0x1b00), 4);
+ PUSH_DATAh(screen->pushbuf, dec->fence->offset);
+ PUSH_DATA (screen->pushbuf, dec->fence->offset);
+ PUSH_DATA (screen->pushbuf, 1);
+ PUSH_DATA (screen->pushbuf, 0xf010);
+ PUSH_KICK (screen->pushbuf);
+
+ PUSH_SPACE(bsp_push, 2 + 12 + 2 + 4 + 3);
+
+...
2014 Jan 23
2
[PATCH v2] nv50, nvc0: clear out RT on a null cbuf
...c0_fb_set_null_rt(push, i);
> + continue;
> + }
> +
> + sf = nv50_surface(fb->cbufs[i]);
> + res = nv04_resource(sf->base.texture);
> + bo = res->bo;
>
> BEGIN_NVC0(push, NVC0_3D(RT_ADDRESS_HIGH(i)), 9);
> PUSH_DATAh(push, res->address + sf->offset);
>
2014 Jun 21
3
[Mesa-dev] [PATCH try 2 2/2] gallium/nouveau: move pushbuf and fences to context
...v50 = container_of(mgr, nv50, base.fence);
> + push = nv50->base.pushbuf;
> +
> + /* we need to do it after possible flush in MARK_RING */
> + *sequence = ++nv50->base.fence.sequence;
> +
> + PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4));
> + PUSH_DATAh(push, nv50->fence.bo->offset + nv50->fence.ofs);
> + PUSH_DATA (push, nv50->fence.bo->offset + nv50->fence.ofs);
> + PUSH_DATA (push, *sequence);
> + PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 |
> + NV50_3D_QUERY_GET_UNK4 |
> +...