search for: pure_instructions

...Thanks! Zach LLVM Code: define <4 x double> @vstore(<4 x double>*) { entry: %1 = load <4 x double>* %0, align 8 ret <4 x double> %1 } ------------------------------------------------------------ Running llvm-32/bin/llc vstore.ll creates: .section __TEXT,__text,regular,pure_instructions .globl _vstore .align 4, 0x90 _vstore: ## @vstore .cfi_startproc ## BB#0: ## %entry pushq %rbp Ltmp2: .cfi_def_cfa_offset 16 Ltmp3: .cfi_offset %rbp, -16 movq %rsp, %rbp Ltmp4: .cfi_def_cfa_register %rbp vmovups (%rdi), %ymm0 popq %rbp r...

The attached .ll files seem equivalent, but the resulting asm from 'opt-fail.ll' causes a crash to webkit. I suspect the usage of registers is wrong, can someone take a look ? $ llc opt-pass.ll -o - .section __TEXT,__text,regular,pure_instructions .globl __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE .align 4, 0x90 __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE: ## @_ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE ## BB#0: pushq %r14 pushq %rbx subq $8, %rsp movq %rsi...

...hift wasn't supposed to be there in the first place? Can you send me a .ii file that produces the __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE function with steps to get the bad IR? -Chris > > $ llc opt-pass.ll -o - > > .section __TEXT,__text,regular,pure_instructions > .globl __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE > .align 4, 0x90 > __ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE: ## @_ZN7WebCore6kolos1ERiS0_PKNS_20RenderBoxModelObjectEPNS_10StyleImageE > ## BB#0: > pushq %r14 > pushq...

...turn res; } - - - - Compiling this with any level of optimization for arm64 gives incorrect code, unless my test case above is triggering some undefined behaviour that I’m not aware of. Other architectures appear to work OK. $ clang -arch arm64 -O1 test.c -S -o - .section __TEXT,__text,regular,pure_instructions .ios_version_min 5, 0 .globl _getVec3 .align 2 _getVec3: ; @getVec3 ; BB#0: b _getVec2 .subsections_via_symbols - - - - I’m happy to file a bug for this, but not sure quite where it belongs - clang, LLVM or direct to Apple. Can someone test the top of tree and...

I think there's a bug somewhere in TableGen for the X86 disassembler emitter. The following test: $ echo "0xF3 0xA5" | ./bin/llvm-mc -disassemble .section __TEXT,__text,regular,pure_instructions movsd (from llvm trunk) 0xF3 is the REP prefix, so the printed instruction should be 'rep movsd', however all that is printed is 'movsd'. It seems that there is an instruction enum for REP_MOVSD, but it isn't emitted in the generated .inc file? Is this a bug/oversight,...

...onstant [6 x i8] c"~Foo\0A\00" @.str1 = private unnamed_addr constant [5 x i8] c"Foo\0A\00" @llvm.global_ctors = appending global [1 x %0] [%0 { i32 65535, void ()* @_GLOBAL__I_a }] define internal void @__cxx_global_var_init() nounwind section "__TEXT,__StaticInit,regular,pure_instructions" { call void @_ZN3FooC1Ev(%class.Foo* @foo) %1 = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.Foo*)* @_ZN3FooD1Ev to void (i8*)*), i8* bitcast (%class.Foo* @foo to i8*), i8* bitcast (i8** @__dso_handle to i8*)) ret void } define linkonce_odr void @_ZN3FooC1Ev(%class.Foo* %this)...

...o common becomes irrelevant. In MachO do you just put these into the .bss section? > Macho has a special zerofill directive (targeted at the BSS section) for this. You can see this by running your example like this: $ llc t.ll -o - -mtriple=i386-apple-darwin10 .section __TEXT,__text,regular,pure_instructions .zerofill __DATA,__bss,_tst1,4,0 ## @tst1 .section __DATA,__data _tst2: ## @tst2 .ascii "\000\001\002\003" -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attach...

...In MachO do you just put these into the .bss section? >> > > Macho has a special zerofill directive (targeted at the BSS section) for this. You can see this by running your example like this: > > $ llc t.ll -o - -mtriple=i386-apple-darwin10 > .section __TEXT,__text,regular,pure_instructions > .zerofill __DATA,__bss,_tst1,4,0 ## @tst1 > .section __DATA,__data > _tst2: ## @tst2 > .ascii "\000\001\002\003" > > I think we should have an 'EmitZeroFill()' and 'EmitASCII()' OutStream methods, the latter t...

...> typedef struct {float v0, v1, v2;} vec3; > > vec2 getVec2(); > > vec3 getVec3() > { > vec2 myVec = getVec2(); > > vec3 res; > res.v0 = myVec.v0; > res.v1 = myVec.v1; > res.v2 = 1; > return res; > } > > .section __TEXT,__text,regular,pure_instructions > .globl _getVec3 > .align 2 > _getVec3: ; @getVec3 > ; BB#0: > stp fp, lr, [sp, #-16]! > mov fp, sp > bl _getVec2 > fmov s2, #1.000000e+00 > ldp fp, lr, [sp], #16 > ret > > > On Mon, May 4, 2015 at 1:19 PM, Simon Taylo...

...ssuming you are on OS X): > ====== > ISYSROOT=$(xcodebuild -sdk macosx -version PlatformPath)/Developer/SDKs/MacOSX10.8.sdk > $(xcrun -find clang) -isysroot $ISYSROOT ror.c -c -S -Os -o - > ====== > > yielding an assembly output of: > ====== > .section __TEXT,__text,regular,pure_instructions > .globl _rotr > _rotr: ## @rotr > .cfi_startproc > ## BB#0: > pushq %rbp > Ltmp2: > .cfi_def_cfa_offset 16 > Ltmp3: > .cfi_offset %rbp, -16 > movq %rsp, %rbp > Ltmp4: > .cfi_def_cfa_register %rbp > movb %sil, %cl >...

...ding" option that can be used to dump out the encodings for every instruction. If you're using clang, this can be accessed with the (intentionally) hidden -mllvm option like so: $ clang t.c -S -o - -mllvm -show-mc-encoding -mkernel -O3 -fomit-frame-pointer .section __TEXT,__text,regular,pure_instructions .globl _tf_bH .align 4, 0x90 _tf_bH: ## @tf_bH ## BB#0: ## %entry ## kill: RSI<def> ESI<kill> movq _last_tf_arg_u at GOTPCREL(%rip), %rax ## encoding: [0x48,0x8b,0x05,A,A,A,A]...

...quot;~Foo\0A\00" > @.str1 = private unnamed_addr constant [5 x i8] c"Foo\0A\00" > @llvm.global_ctors = appending global [1 x %0] [%0 { i32 65535, void ()* @_GLOBAL__I_a }] > > define internal void @__cxx_global_var_init() nounwind section "__TEXT,__StaticInit,regular,pure_instructions" { >  call void @_ZN3FooC1Ev(%class.Foo* @foo) >  %1 = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%class.Foo*)* @_ZN3FooD1Ev to void (i8*)*), i8* bitcast (%class.Foo* @foo to i8*), i8* bitcast (i8** @__dso_handle to i8*)) >  ret void > } > > define linkonce_odr void @_...

.... In MachO do you just put these into the .bss section? > > > Macho has a special zerofill directive (targeted at the BSS section) for > this. You can see this by running your example like this: > > $ llc t.ll -o - -mtriple=i386-apple-darwin10 > .section __TEXT,__text,regular,pure_instructions > .zerofill __DATA,__bss,_tst1,4,0 ## @tst1 > .section __DATA,__data > _tst2: ## @tst2 > .ascii "\000\001\002\003" > I think we should have an 'EmitZeroFill()' and 'EmitASCII()' OutStream methods, the latter to deal w...

...ype: application/octet-stream Size: 447 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100831/9782fea6/attachment-0002.obj> -------------- next part -------------- $ opt -std-compile-opts unopt-pass.ll -o - | llc -o - .section __TEXT,__text,regular,pure_instructions .globl __ZN7WebCore15GraphicsContext19roundToDevicePixelsERKNS_9FloatRectE .align 4, 0x90 __ZN7WebCore15GraphicsContext19roundToDevicePixelsERKNS_9FloatRectE: ## @_ZN7WebCore15GraphicsContext19roundToDevicePixelsERKNS_9FloatRectE ## BB#0: subq $24, %rsp movq %rsi, %rdx movl $0, 16(%rsp) movl...

I notice llvm provides both ordered and unordered variants of floating-point comparison. Which of these is the right one to use by default? I suppose the two criteria would be, in order of importance: 1. Which is more efficient (more directly maps to typical hardware)? 2. Which is more familiar (more like the way C and Fortran do it)?

...al hardware)? You can figure this out by looking at the output of llc: $ cat test.ll define i1 @less(double %x, double %y) nounwind readnone { entry: %0 = fcmp ult double %x, %y ; <i1> [#uses=1] ret i1 %0 } $ Debug/bin/llc <test.ll .section __TEXT,__text,regular,pure_instructions .globl _less .align 4, 0x90 _less: ## @less ## BB#0: ## %entry movsd 4(%esp), %xmm0 ucomisd 12(%esp), %xmm0 sbbb %al, %al andb $1, %al ret > 2. Which is more familiar (more like the way C and Fortran do it)? You can use htt...

On 13 August 2012 12:02, Andrew Ruef <awruef at umd.edu> wrote: > I think there's a bug somewhere in TableGen for the X86 disassembler > emitter. The following test: > > $ echo "0xF3 0xA5" | ./bin/llvm-mc -disassemble > .section __TEXT,__text,regular,pure_instructions > movsd > > (from llvm trunk) > > 0xF3 is the REP prefix, so the printed instruction should be 'rep > movsd', however all that is printed is 'movsd'. It seems that there is > an instruction enum for REP_MOVSD, but it isn't emitted in the > generat...

..._bits)); } ====== Then compile with (assuming you are on OS X): ====== ISYSROOT=$(xcodebuild -sdk macosx -version PlatformPath)/Developer/SDKs/MacOSX10.8.sdk $(xcrun -find clang) -isysroot $ISYSROOT ror.c -c -S -Os -o - ====== yielding an assembly output of: ====== .section __TEXT,__text,regular,pure_instructions .globl _rotr _rotr: ## @rotr .cfi_startproc ## BB#0: pushq %rbp Ltmp2: .cfi_def_cfa_offset 16 Ltmp3: .cfi_offset %rbp, -16 movq %rsp, %rbp Ltmp4: .cfi_def_cfa_register %rbp movb %sil, %cl rorl %cl, %edi <==== Rotate instructi...

in C or C++, how can I get clang/llvm to try and do a "rotate". (want to test this code in the mips16 port) i.e. emit rotr node. tia. reed

...itional problem where undefined results are being introduced First to show what I'm discussing: test.cpp: __attribute((noinline, naked)) int NakedTest(int value, int value2) { asm(""); } Example using svn r167616 of clang/llvm: clang -S test.cpp .section __TEXT,__text,regular,pure_instructions .globl __Z9NakedTestii .align 4, 0x90 __Z9NakedTestii: ## @_Z9NakedTestii .cfi_startproc ## BB#0: ## %entry movl %edi, -8(%rbp) movl %esi, -12(%rbp) ## InlineAsm Start ## InlineAsm End ud2 .cfi_endproc The first two highlighted lines...