search for: ptrb

...f-info" and for printing sets of alias "opt -analyze -aa-eval -print-alias-sets" gives me the results, that in main function variables %a, %0, %2, %4 alias. However I expected from Alias Analysis to indicate that pointers which point to same memory location alias, namely, %ptra and %ptrb. I learnt from your last messages, that "A pointer is just a variable containing memory address, so pointer itself will never alias with other pointers, but the ‘pointee’ will alias with other memory addresses." My goal is to find sets of pointers, that point to the same memory location...

...lem. You should also take a look at the test.ll and test_clean.ll > and make sure you fully understand what the code representation > means. As I noted in the other thread, your example is to simple, > after the stack locations are promoted to registers, there is no > "ptra/ptrb" that could alias anymore. > > I hope this helps. > > Cheers, > Johannes > > > > On 12/14, Артём Вопилов via llvm-dev wrote: >> Dear LLVM developers, >> >> My name is Artem Vopilov, I am a student at TU Darmstadt. I am writing to you again to...

...alyze -aa-eval -print-all-alias-modref-info" and for printing sets of alias "opt -analyze -aa-eval -print-alias-sets". I execute these commands on the small test program I attached to this email. If you take a look at it, it will be obvious, that variables "ptra" and "ptrb" alias. However, the results of Alias Analysis do not indicate, that these variable alias. I would like to ask you, if it is possible to change the source code of Alias Analysis, so that it will show that "ptra" and "ptrb" variables from the test program alias. I am lookin...

...Uses = [R0] in > + def ATOMIC_LOAD_ADD_I32 : Pseudo< > > The "let Uses = [R0]" is not needed. The pseudo instruction will be > expanded like this later: > > + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) > + .addReg(ptrA).addReg(ptrB); > + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) > + .addReg(incr).addReg(dest); > + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) > + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB); > > The second instruction defines R0 and the 3...

...+ def ATOMIC_LOAD_ADD_I32 : Pseudo< >> >> The "let Uses = [R0]" is not needed. The pseudo instruction will be >> expanded like this later: >> >> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) >> + .addReg(ptrA).addReg(ptrB); >> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) >> + .addReg(incr).addReg(dest); >> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) >> + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB); >> >> The second instructi...

...{ + let Uses = [CR0] in { + let Uses = [R0] in + def ATOMIC_LOAD_ADD_I32 : Pseudo< The "let Uses = [R0]" is not needed. The pseudo instruction will be expanded like this later: + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) + .addReg(ptrA).addReg(ptrB); + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) + .addReg(incr).addReg(dest); + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB); The second instruction defines R0 and the 3rd reads R0 which is enough...

...MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32 || + MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) { + bool is64bit = MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64; + + unsigned dest = MI->getOperand(0).getReg(); + unsigned ptrA = MI->getOperand(1).getReg(); + unsigned ptrB = MI->getOperand(2).getReg(); + unsigned incr = MI->getOperand(3).getReg(); + + MachineBasicBlock *loopMBB = new MachineBasicBlock(LLVM_BB); + MachineBasicBlock *exitMBB = new MachineBasicBlock(LLVM_BB); + + MachineFunction *F = BB->getParent(); + F->getBasicBlockList().i...

...: Pseudo< > >> > >> The "let Uses = [R0]" is not needed. The pseudo instruction will be > >> expanded like this later: > >> > >> + BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest) > >> + .addReg(ptrA).addReg(ptrB); > >> + BuildMI(BB, TII->get(is64bit ? PPC::ADD4 : PPC::ADD8), PPC::R0) > >> + .addReg(incr).addReg(dest); > >> + BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX)) > >> + .addReg(PPC::R0).addReg(ptrA).addReg(ptrB); > >> >...

...MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32 || + MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) { + bool is64bit = MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64; + + unsigned dest = MI->getOperand(0).getReg(); + unsigned ptrA = MI->getOperand(1).getReg(); + unsigned ptrB = MI->getOperand(2).getReg(); + unsigned incr = MI->getOperand(3).getReg(); + + MachineBasicBlock *loopMBB = new MachineBasicBlock(LLVM_BB); + MachineBasicBlock *exitMBB = new MachineBasicBlock(LLVM_BB); + + MachineFunction *F = BB->getParent(); + F->getBasicBlockList().i...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32 || + MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) { + bool is64bit = MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64; + + unsigned dest = MI->getOperand(0).getReg(); + unsigned ptrA = MI->getOperand(1).getReg(); + unsigned ptrB = MI->getOperand(2).getReg(); + unsigned incr = MI->getOperand(3).getReg(); + + MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(It, loopMBB); + F->insert(It, exitMBB);...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32 || + MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64) { + bool is64bit = MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64; + + unsigned dest = MI->getOperand(0).getReg(); + unsigned ptrA = MI->getOperand(1).getReg(); + unsigned ptrB = MI->getOperand(2).getReg(); + unsigned incr = MI->getOperand(3).getReg(); + + MachineBasicBlock *loopMBB = new MachineBasicBlock(LLVM_BB); + MachineBasicBlock *exitMBB = new MachineBasicBlock(LLVM_BB); + + MachineFunction *F = BB->getParent(); + F->getBasicBlockList().i...

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...om a rather simple *.c program. ---------------------------------- ; ModuleID = 'ptralias.bc' target endian = little target pointersize = 32 target triple = "i686-pc-linux-gnu" deplibs = [ "c", "crtend" ] %.str_1 = internal constant [25 x sbyte] c"ptra=0x ptrb=0x ptrc=0x\0A\00" ; <[25 x sbyte]*> [#uses=1] %ptr = weak global void ()* null ; <void ()**> [#uses=0] implementation ; Functions: declare int %printf(sbyte*, ...) void %foo1() { ret void } void %foo2() { ret void } int %main(int %argc, sbyte** %argv) { entry: %data_b =...

Hi, We, IBM XL Fortran compiler team, is interested in representing Fortran alias information in LLVM IR. We use the XL Fortran frontend to emit LLVM IR that includes alias information to feed to the LLVM in order to create object files. For the Fortran alias representation in LLVM IR, we considered both TBAA and ScopeAlias/NoAlias metadata approaches, we think that the ScopeAlias/NoAlias

...t; ---------------------------------- > ; ModuleID = 'ptralias.bc' > target endian = little > target pointersize = 32 > target triple = "i686-pc-linux-gnu" > deplibs = [ "c", "crtend" ] > %.str_1 = internal constant [25 x sbyte] c"ptra=0x ptrb=0x > ptrc=0x\0A\00" ; <[25 x sbyte]*> [#uses=1] > %ptr = weak global void ()* null ; <void ()**> [#uses=0] > > implementation ; Functions: > > declare int %printf(sbyte*, ...) > > void %foo1() { > ret void > } &gt...