search for: ptr

...19BA1 is: >> >> 76719BA1 push ebp >> 76719BA2 mov ebp,esp >> 76719BA4 sub esp,20h >> 76719BA7 and esp,0FFFFFFF0h >> 76719BAA fld st(0) >> 76719BAC fst dword ptr [esp+18h] >> 76719BB0 fistp qword ptr [esp+10h] >> 76719BB4 fild qword ptr [esp+10h] >> 76719BB8 mov edx,dword ptr [esp+18h] >> 76719BBC mov eax,dword ptr [esp+10h] >> 76719BC0 test eax,ea...

...n the LLVM IR. >> >> The code at 76719BA1 is: >> >> 76719BA1 push ebp >> 76719BA2 mov ebp,esp >> 76719BA4 sub esp,20h >> 76719BA7 and esp,0FFFFFFF0h >> 76719BAA fld st(0) >> 76719BAC fst dword ptr [esp+18h] >> 76719BB0 fistp qword ptr [esp+10h] >> 76719BB4 fild qword ptr [esp+10h] >> 76719BB8 mov edx,dword ptr [esp+18h] >> 76719BBC mov eax,dword ptr [esp+10h] >> 76719BC0 test eax,eax >> 76719BC2 je 76719DC...

...trigger_type" => TaskScheduler::DAILY, "type" => { "days_interval" => 1 } } ts = TaskScheduler.new ts.new_work_item("foo",trigger) I did find two things that I thought might solve the problem but didn''t seem to help. The first is to call ptr->pITS->Release() after the NewWorkItem() call. I''m not sure if that''s necessary or not, but they do that in their sample program on MSDN. The second thing I tried was adding CoUninitialize() if the call to NewWorkItem() failed before raising an exception. Neither helped....

Compile the following functions with "-O3 -target i386-win32" (see <https://godbolt.org/z/exmjWY>): __int64 __fastcall div(__int64 foo, __int64 bar) { return foo / bar; } On the left the generated code; on the right the expected, properly optimised code: push dword ptr [esp + 16] | push dword ptr [esp + 16] | push dword ptr [esp + 16] | push dword ptr [esp + 16] | call __alldiv | jmp __alldiv ret 16 | __int64 __fastcall mod(__int64 foo, __int64 bar) { retu...

...013C1428 lea eax,[ebp-48h] 013C142B push eax 013C142C lea ecx,[ebp-138h] 013C1432 push ecx 013C1433 call fetch (13C11D6h) 013C1438 add esp,8 // Copy result to another temporary vairable. 013C143B mov edx,dword ptr [eax] 013C143D mov dword ptr [ebp-150h],edx 013C1443 mov ecx,dword ptr [eax+4] 013C1446 mov dword ptr [ebp-14Ch],ecx 013C144C mov edx,dword ptr [eax+8] 013C144F mov dword ptr [ebp-148h],edx 013C1455 mov eax,dword ptr [eax...

...d by the X86ISelSimple which is only 8 instructions... it seems the compare is being generated twice in two different ways with the pattern selector?! I also attached the diff of my current version m. internal void %EvaluatePoint3D65() { EntryBlock: store float 0.000000e+000, float* getelementptr ([4 x float]* cast (<4 x float>* %_ARGB56 to [4 x float]*), int 0, int 0) store float 0.000000e+000, float* getelementptr ([4 x float]* cast (<4 x float>* %_ARGB56 to [4 x float]*), int 0, int 1) store float 0.000000e+000, float* getelementptr ([4 x float]* cast (<4 x float>*...

--- include/share/alloc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/share/alloc.h b/include/share/alloc.h index 914de9ba..63878db0 100644 --- a/include/share/alloc.h +++ b/include/share/alloc.h @@ -168,7 +168,7 @@ static inline void *safe_realloc_add_2op_(void *ptr, size_t size1, size_t size2) free(ptr); return 0; } - return realloc(ptr, size2); + return safe_realloc_(ptr, size2); } static inline void *safe_realloc_add_3op_(void *ptr, size_t size1, size_t size2, size_t size3) -- 2.17.1

...opefully fixes it... diff --git a/libswfdec/swfdec_bits.c b/libswfdec/swfdec_bits.c index c8a5062..8ec6936 100644 --- a/libswfdec/swfdec_bits.c +++ b/libswfdec/swfdec_bits.c @@ -307,11 +307,9 @@ swfdec_bits_get_float (SwfdecBits * b) SWFDEC_BYTES_CHECK (b, 4); - conv.i = *((gint32 *) b->ptr); + conv.i = (b->ptr[3] << 24) | (b->ptr[2] << 16) | (b->ptr[1] << 8) | b->ptr[0]; b->ptr += 4; - conv.i = GINT32_FROM_LE (conv.i); - return conv.f; } @@ -323,40 +321,30 @@ swfdec_bits_get_float (SwfdecBits * b) * use this command line: * python -c...

These changes are based on Jason's latest hmm branch. Patch 1 was previously posted here [1] but was dropped from the orginal series. Hopefully, the tests will reduce concerns about edge conditions. I'm sure more tests could be usefully added but I thought this was a good starting point. [1] https://lore.kernel.org/linux-mm/20190726005650.2566-6-rcampbell at nvidia.com/ Ralph Campbell

...opefully fixes it... diff --git a/libswfdec/swfdec_bits.c b/libswfdec/swfdec_bits.c index c8a5062..8ec6936 100644 --- a/libswfdec/swfdec_bits.c +++ b/libswfdec/swfdec_bits.c @@ -307,11 +307,9 @@ swfdec_bits_get_float (SwfdecBits * b) SWFDEC_BYTES_CHECK (b, 4); - conv.i = *((gint32 *) b->ptr); + conv.i = (b->ptr[3] << 24) | (b->ptr[2] << 16) | (b->ptr[1] << 8) | b->ptr[0]; b->ptr += 4; - conv.i = GINT32_FROM_LE (conv.i); - return conv.f; } @@ -323,40 +321,30 @@ swfdec_bits_get_float (SwfdecBits * b) * use this command line: * python -c...

...notations to VarDecls and FieldDecls, and write this modified AST out to a file. I notice that when I use clang to compile this file I get different code then when I use the source directly. In both cases I'm compiling with -O4. Can anyone explain this? Thanks define i32 @somefunc(i32 (i32)* %ptr) nounwind uwtable { entry: %ptr.addr = alloca i32 (i32)*, align 8 store i32 (i32)* %ptr, i32 (i32)** %ptr.addr, align 8, !tbaa !0 %ptr.addr1 = bitcast i32 (i32)** %ptr.addr to i8* call void @llvm.var.annotation(i8* %ptr.addr1, i8* getelementptr inbounds ([11 x i8]* @.str, i64 0, i64 0), i8*...

...============================================ > > --- libspeex/preprocess.c (revision 13983) > > +++ libspeex/preprocess.c (arbetskopia) > > @@ -1126,16 +1126,16 @@ > > break; > > > > case SPEEX_PREPROCESS_SET_PROB_START: > > - *(spx_int32_t*)ptr = MIN32(Q15_ONE,MAX32(0, *(spx_int32_t*) > > ptr)); > > - st->speech_prob_start = DIV32_16(MULT16_16(32767,* > > (spx_int32_t*)ptr), 100); > > + *(spx_int32_t*)ptr = MIN32(100,MAX32(0, *(spx_int32_t*)ptr)); > > + st->speech_prob_start = DIV32_16(...

...roll the loop, which > GCC does not do, but the addressing code is a constant repetition of these > three instructions: > > imull $7, %ecx, %edx > movl %eax, %esi > addl %edx, %esi Yup, this is an issue of simple "peephole expansion" of the getelementptr instruction. > All but the first occurrance do nothing but put the same address into %esi > that was already there to being with, and does it with an expensive multiply > at that. GCC correctly creates a suitable induction variable and strength > reduces the multiplication down to...

...x i8] c"E%d\00", align 1 @bmask = internal unnamed_addr constant [17 x i16] [i16 -1, i16 -2, i16 -4, i16 -8, i16 -16, i16 -32, i16 -64, i16 -128, i16 -256, i16 -512, i16 -1024, i16 -2048, i16 -4096, i16 -8192, i16 -16384, i16 -32768, i16 0], align 2 define i8* @_ldtoa_r(%struct._reent* %ptr, double %d, i32 %mode, i32 %ndigits, i32* nocapture %decpt, i32* nocapture %sign, i8** %rve) nounwind { entry: %ai.i.i.i.i = alloca [13 x i16], align 2 %bi.i.i.i.i = alloca [13 x i16], align 2 %f.i.i = alloca [10 x i16], align 2 %y.i = alloca [13 x i16], align 2 %t.i = alloca [13 x i16],...

...ut the generated assembly code only uses 2 registers. How to enable it to use all 8? Also can i control the ordering like after R_0 can i use R_5 without changes in registerinfo.td? What changes are required here? either in scheduling or register allocation phases? P_2048B_LOAD_DWORD R_0, Pword ptr [rip + b] P_2048B_LOAD_DWORD R_1, Pword ptr [rip + c] P_2048B_VADD R_0, R_1, R_0 P_2048B_STORE_DWORD Pword ptr [rip + a], R_0 P_2048B_LOAD_DWORD R_0, Pword ptr [rip + b+2048] P_2048B_LOAD_DWORD R_1, Pword ptr [rip + c+2048] P_2048B_VADD R_0, R_1, R_0 P_2048B_STORE_DWORD Pword ptr [rip + a+2048], R_...

...ere was a similar discussion about this issue in the past as well, but seems it is not settled yet. What should the semantics of nonnull be? I listed a few optimizations that are relevant with this issue. 1. Propagating nonnull attribute to callee's arg ( https://godbolt.org/z/-cVsVP ) g(i8* ptr) { f(nonnull ptr); } => g(i8* nonnull ptr) { f(nonnull ptr); } This is correct if f(nonnull null) is UB. If ptr == null, f(nonnull null) should have raised UB, so ptr shouldn't be null. However, this transformation is incorrect if f(nonnull null) is equivalent to f(poison). If f was an empt...

...-------------- Index: libspeex/preprocess.c =================================================================== --- libspeex/preprocess.c (revision 13983) +++ libspeex/preprocess.c (arbetskopia) @@ -1126,16 +1126,16 @@ break; case SPEEX_PREPROCESS_SET_PROB_START: - *(spx_int32_t*)ptr = MIN32(Q15_ONE,MAX32(0, *(spx_int32_t*)ptr)); - st->speech_prob_start = DIV32_16(MULT16_16(32767,*(spx_int32_t*)ptr), 100); + *(spx_int32_t*)ptr = MIN32(100,MAX32(0, *(spx_int32_t*)ptr)); + st->speech_prob_start = DIV32_16(MULT16_16(Q15ONE,*(spx_int32_t*)ptr), 100); bre...

declare i8 @llvm.atomic.load.max.i8.p0i8( i8* <ptr>, i8 <delta> ) declare i16 @llvm.atomic.load.max.i16.p0i16( i16* <ptr>, i16 <delta> ) declare i32 @llvm.atomic.load.max.i32.p0i32( i32* <ptr>, i32 <delta> ) declare i64 @llvm.atomic.load.max.i64.p0i64( i64* <ptr>, i64 <delta> ) declare i8 @llvm.a...

...el but I screwed up when trying out the really big array. You're right, it does clean it up except for the multiplication. So LoopStrengthReduce is not ready for prime time and doesn't actually get used? I might consider whipping it into shape. Does it still have to handle getelementptr in its full generality? Chris Lattner wrote: > On Mon, 21 Feb 2005, Jeff Cohen wrote: > >> I noticed that fourinarow is one of the programs in which LLVM is >> much slower than GCC, so I decided to take a look and see why that is >> so. The program has many loops that l...

Couple of other problematic transforms: # undef refinement After thinking about this a bit, I think undef refinement happens a lot more often than I initially thought, and it happens implicitly. Consider the following case: void @foo(int* ptr) available_externally { int k = *ptr; if (k == 1 && k == 2) print("X"); } void main() { int* ptr = malloc(); *ptr = 200; @foo(ptr) } => void @foo(int* ptr) readnone available_externally { //int k = *ptr; //if (false) print("X");...