Displaying 13 results from an estimated 13 matches for "ptr4".
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2013 Jan 29
2
[LLVMdev] Apparent indeterminism in PreVerifier
...see the
following:
Common predecessor:
*** IR Dump After Loop-Closed SSA Form Pass ***
for.body.us68: ; preds =
%for.body.lr.ph.us81, %for.body.us68
%arrayidx.us70.phi = phi i8* [ %buf.0.ph, %for.body.lr.ph.us81 ], [
%arrayidx.us70.inc, %for.body.us68 ]
%add.ptr4.us72.phi = phi i8* [ %add.ptr4.us72.gep, %for.body.lr.ph.us81 ],
[ %add.ptr4.us72.inc, %for.body.us68 ]
%i.043.us69 = phi i32 [ 0, %for.body.lr.ph.us81 ], [ %inc.us73,
%for.body.us68 ]
...
LV: Found a vectorizable loop (8) in core_state.i
LV: Adding RT check for range: %add.ptr4.us72.phi = ph...
2013 Jan 29
2
[LLVMdev] Apparent indeterminism in PreVerifier
...* IR Dump After Loop-Closed SSA Form Pass ***
>> for.body.us68: ; preds =
>> %for.body.lr.ph.us81, %for.body.us68
>> %arrayidx.us70.phi = phi i8* [ %buf.0.ph, %for.body.lr.ph.us81 ], [
>> %arrayidx.us70.inc, %for.body.us68 ]
>> %add.ptr4.us72.phi = phi i8* [ %add.ptr4.us72.gep,
>> %for.body.lr.ph.us81 ], [ %add.ptr4.us72.inc, %for.body.us68 ]
>> %i.043.us69 = phi i32 [ 0, %for.body.lr.ph.us81 ], [ %inc.us73,
>> %for.body.us68 ]
>> ...
>>
>> LV: Found a vectorizable loop (8) in core_state.i
>...
2013 Jan 29
0
[LLVMdev] Apparent indeterminism in PreVerifier
...sor:
>
> *** IR Dump After Loop-Closed SSA Form Pass ***
> for.body.us68: ; preds =
> %for.body.lr.ph.us81, %for.body.us68
> %arrayidx.us70.phi = phi i8* [ %buf.0.ph, %for.body.lr.ph.us81 ], [
> %arrayidx.us70.inc, %for.body.us68 ]
> %add.ptr4.us72.phi = phi i8* [ %add.ptr4.us72.gep,
> %for.body.lr.ph.us81 ], [ %add.ptr4.us72.inc, %for.body.us68 ]
> %i.043.us69 = phi i32 [ 0, %for.body.lr.ph.us81 ], [ %inc.us73,
> %for.body.us68 ]
> ...
>
> LV: Found a vectorizable loop (8) in core_state.i
> LV: Adding RT check...
2013 Jan 29
0
[LLVMdev] Apparent indeterminism in PreVerifier
...fter Loop-Closed SSA Form Pass ***
> >> for.body.us68: ; preds =
> >> %for.body.lr.ph.us81, %for.body.us68
> >> %arrayidx.us70.phi = phi i8* [ %buf.0.ph, %for.body.lr.ph.us81 ], [
> >> %arrayidx.us70.inc, %for.body.us68 ] %add.ptr4.us72.phi = phi i8* [
> >> %add.ptr4.us72.gep,
> >> %for.body.lr.ph.us81 ], [ %add.ptr4.us72.inc, %for.body.us68 ]
> >> %i.043.us69 = phi i32 [ 0, %for.body.lr.ph.us81 ], [ %inc.us73,
> >> %for.body.us68 ]
> >> ...
> >>
> >> LV: Found...
2013 Jan 29
1
[LLVMdev] Apparent indeterminism in PreVerifier
...losed SSA Form Pass ***
>>>> for.body.us68: ; preds =
>>>> %for.body.lr.ph.us81, %for.body.us68
>>>> %arrayidx.us70.phi = phi i8* [ %buf.0.ph, %for.body.lr.ph.us81 ], [
>>>> %arrayidx.us70.inc, %for.body.us68 ] %add.ptr4.us72.phi = phi i8* [
>>>> %add.ptr4.us72.gep,
>>>> %for.body.lr.ph.us81 ], [ %add.ptr4.us72.inc, %for.body.us68 ]
>>>> %i.043.us69 = phi i32 [ 0, %for.body.lr.ph.us81 ], [ %inc.us73,
>>>> %for.body.us68 ]
>>>> ...
>>>>
>>...
2013 Jan 07
0
[LLVMdev] instruction scheduling issue
Liu,
This is likely a better solution for you - you do not want to mess with
the scheduler unless you really have to ;)
Sergei
---
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Krzysztof Parzyszek
> Sent:
2017 Dec 19
4
A code layout related side-effect introduced by rL318299
...addr #2
@i = global i8 0, align 1
define i8* @_Z1gPcS_S_(i8* nocapture readonly %d, i8* %h, i8* readnone
returned %p3) local_unnamed_addr #3 {
entry:
br label %while.cond
while.cond: ; preds = %while.body,
%entry
%h.addr.0 = phi i8* [ %h, %entry ], [ %add.ptr4, %while.body ]
%d.addr.0 = phi i8* [ %d, %entry ], [ %add.ptr3, %while.body ]
%cmp = icmp ugt i8* %h.addr.0, @i
br i1 %cmp, label %while.end, label %while.body
while.body: ; preds = %while.cond
%0 = bitcast i8* %d.addr.0 to i64*
%1 = load i64, i64* %...
2017 Dec 19
2
A code layout related side-effect introduced by rL318299
...nocapture readonly %d, i8* %h, i8* readnone
>> returned %p3) local_unnamed_addr #3 {
>> entry:
>> br label %while.cond
>>
>> while.cond: ; preds = %while.body,
>> %entry
>> %h.addr.0 = phi i8* [ %h, %entry ], [ %add.ptr4, %while.body ]
>> %d.addr.0 = phi i8* [ %d, %entry ], [ %add.ptr3, %while.body ]
>> %cmp = icmp ugt i8* %h.addr.0, @i
>> br i1 %cmp, label %while.end, label %while.body
>>
>> while.body: ; preds = %while.cond
>> %0 =...
2013 Jan 07
4
[LLVMdev] instruction scheduling issue
On 1/7/2013 2:15 PM, Xu Liu wrote:
>
> This would be ideal. How can I do the instrumentation pass after the
> instruction scheduling?
You could derive your own class from TargetPassConfig, and add the
annotation pass in YourDerivedTargetPassConfig::addPreEmitPass. This
will add your annotation pass very late, just before the final code is
emitted. If you're using the X86 target,
2017 Apr 28
3
Store unswitch
Hi Danny,
Thanks for that :) However I've just updated the prototype patch to NewGVN
and it didn't need any API changes - all I rely on is GVNExpression.
Hongbin,
I wanted to explain a little about what GVNSink can currently do, what it
was designed for and hopefully how to make it handle your testcase.
*Background*
Common code sinking is more difficult to efficently do than one might
2011 Aug 19
1
[LLVMdev] LLVM: Very simple question
Hi, guys. I'm a newbie to LLVM and have a very simple question.
Which instructions should I use (in terms of IRBuilder calls) to allocate an
array of bytes in stack (alloca?), then to work with it (from a given
offset) as with integer (bitcast?). I mean something like that:
unsigned char var[8];
unsigned int offset = 3;
int val = *(int*)(&var+offset); /* read */
*(int*)(&var+offset)
2004 Aug 24
5
MMX/mmxext optimisations
quite some speed improvement indeed.
attached the updated patch to apply to svn/trunk.
j
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2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...; preds = %lor.lhs.false21
%4 = load i16* %pe, align 2, !tbaa !5
%cmp29 = icmp eq i16 %4, 0
br i1 %cmp29, label %if.end32, label %if.then31
if.then31: ; preds = %lor.lhs.false26, %lor.lhs.false21, %lor.lhs.false, %if.then11
%incdec.ptr42.i = getelementptr inbounds i16* %y, i32 1
%scevgep.i = getelementptr i16* %y, i32 9
store i16 0, i16* %y, align 2, !tbaa !5
%incdec.ptr.i2 = getelementptr inbounds i16* %y, i32 2
store i16 0, i16* %incdec.ptr42.i, align 2, !tbaa !5
%incdec.ptr.1.i3 = getelementptr inbounds i16* %y, i32 3...