search for: ptr3

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2002 Sep 14
1
[LLVMdev] MP1: Gelementptr question
The following is legal LLVM code in which ptr, ptr2, and ptr3 are all aliases: %struct = type { int, int } implementation int %p() { %ptr1 = alloca %struct %ptr2 = getelementptr %struct* %ptr1 %ptr3 = getelementptr %struct* %ptr2, uint 0 %pint = getelementptr %struct* %ptr3, uint 0, ubyte 0 %rval = load int* %pint ret int %rval } Should our pa...
2017 Dec 19
4
A code layout related side-effect introduced by rL318299
...apture readonly %d, i8* %h, i8* readnone returned %p3) local_unnamed_addr #3 { entry: br label %while.cond while.cond: ; preds = %while.body, %entry %h.addr.0 = phi i8* [ %h, %entry ], [ %add.ptr4, %while.body ] %d.addr.0 = phi i8* [ %d, %entry ], [ %add.ptr3, %while.body ] %cmp = icmp ugt i8* %h.addr.0, @i br i1 %cmp, label %while.end, label %while.body while.body: ; preds = %while.cond %0 = bitcast i8* %d.addr.0 to i64* %1 = load i64, i64* %0, align 1 %2 = bitcast i8* %h.addr.0 to i64* store i64 %1, i...
2017 Dec 19
2
A code layout related side-effect introduced by rL318299
...nnamed_addr #3 { >> entry: >> br label %while.cond >> >> while.cond: ; preds = %while.body, >> %entry >> %h.addr.0 = phi i8* [ %h, %entry ], [ %add.ptr4, %while.body ] >> %d.addr.0 = phi i8* [ %d, %entry ], [ %add.ptr3, %while.body ] >> %cmp = icmp ugt i8* %h.addr.0, @i >> br i1 %cmp, label %while.end, label %while.body >> >> while.body: ; preds = %while.cond >> %0 = bitcast i8* %d.addr.0 to i64* >> %1 = load i64, i64* %0, align 1 &...
2020 Jun 19
2
Aliasing and forwarding optimization
----Snip-- struct st1{ int a; }; struct st2{ int b; }; struct st { struct st1 obj1; struct st2 obj2; }Obj; int test1(struct st1 * ptr1 , struct st2 * ptr2, struct st2 *ptr3) { ptr1->a = 10; *ptr3 = *ptr2; return ptr1->a; } --Snip--- For the above case GCC is able to store forward the value 10 to the return place. LLVM is not doing this. GCC https://godbolt.org/z/FCjCXy LLVM https://godbolt.org/z/TFgnig My understanding is that under strict aliasing rules...
2018 Mar 21
0
Finding which registers the operand of a load maps to
​Appreciate all of the quick responses to my ridiculous questions so far. Hoping this one attracts similarly good dis​cussion! Let's say I have the following series of instructions: %a = load i32, i32* %ptr1 %b = load i32, i32* %ptr2 %c = add i32 %a, %b store i32 %c, i32* %ptr3 This gets compiled (roughly) to mov eax, dword ptr [rsp - 4] add eax, dword ptr [rsp - 8] mov dword ptr [rsp - 12], eax In an opt pass, I would like to replace this series of four instructions with a single intrinsic, @llvm.cache.add, which will represent an add performed in the cache:...
2018 Apr 18
1
[RFC] Making GVN able to visit the same block more than once
...anslation), not the one we eventually found it in. With this GVN then goes on to optimise this function exactly as we want. However we then get problems elsewhere. The problem ============ Let's take a look at this function: define i32 @multiple_path_test(i32* %ptr1, i32* %ptr2, i32* %ptr3) { entry: %val1 = load i32, i32* %ptr1, align 4 %val2 = load i32, i32* %ptr2, align 4 %val3 = load i32, i32* %ptr3, align 4 %cmp1 = icmp slt i32 %val1, %val2 br i1 %cmp1, label %a, label %b a: %cmp2 = icmp slt i32 %val1, %val3 br i1 %cmp2, label %end, label %b b:...
2017 Apr 28
3
Store unswitch
Hi Danny, Thanks for that :) However I've just updated the prototype patch to NewGVN and it didn't need any API changes - all I rely on is GVNExpression. Hongbin, I wanted to explain a little about what GVNSink can currently do, what it was designed for and hopefully how to make it handle your testcase. *Background* Common code sinking is more difficult to efficently do than one might
2004 Aug 24
5
MMX/mmxext optimisations
quite some speed improvement indeed. attached the updated patch to apply to svn/trunk. j -------------- next part -------------- A non-text attachment was scrubbed... Name: theora-mmx.patch.gz Type: application/x-gzip Size: 8648 bytes Desc: not available Url : http://lists.xiph.org/pipermail/theora-dev/attachments/20040824/5a5f2731/theora-mmx.patch-0001.bin
2012 Apr 17
3
[LLVMdev] InstCombine adds bit masks, confuses self, others
On Tue, Apr 17, 2012 at 1:36 PM, Rafael Espíndola < rafael.espindola at gmail.com> wrote: > > I am not sure how best to fix this. If possible, InstCombine's > canonicalization shouldn't hide arithmetic progressions behind bit masks. > At least, it seems these transformations should be disabled unless (X >> > C).hasOneUse(). They aren't exactly optimizations.
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...2 11 %scevgep.i728.i = getelementptr [13 x i16]* %u.i, i32 0, i32 12 %349 = add i32 %ndigs.31018.i, 1 br label %for.body302.i for.body302.i: ; preds = %eshup1.exit.i, %for.body302.lr.ph.i %s.2963.i = phi i8* [ %s.11019.i, %for.body302.lr.ph.i ], [ %incdec.ptr317.i, %eshup1.exit.i ] %k.2962.i = phi i32 [ 0, %for.body302.lr.ph.i ], [ %inc319.i, %eshup1.exit.i ] br label %for.body.i734.i for.body.i734.i: ; preds = %if.end.i752.i, %for.body302.i %i.025.i730.i = phi i32 [ 2, %for.body302.i ], [ %inc.i750.i, %if.end.i752...