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...d N. Abu-Rmaileh ACM Transactions on Architecture and Code Optimization (TACO). vol. 10, issue 3, Article 14 (Sept. 2013) http://dx.doi.org/10.1145/2512432 Regards Ghassan Shobaki, PH.D Assistant Professor Department of Computer Science Princess Sumaya University for Technology g dot shobaki at psut dot edu dot jo -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131116/939a8ed4/attachment.html>

...doing that. Our work on pre-allocation instruction scheduling with register pressure minimization will be published soon, but if you would like to get an idea about my previous work on scheduling using branch-and-bound enumeration, you can find it on our school's research web page: http://www.psut.edu.jo/research/index.html?fs=publications/drpub/ghassanshobakic.htm   Since the approach is fundamentally different from the heuristic approach used in LLVM's scheduler (and probably all schedulers found in production compilers), it will be hard to gain an interesting insight through a top-do...

On Sep 23, 2011, at 6:16 AM, Ghassan Shobaki wrote: > Hi Andrew, > > What we have is not a patch to any of LLVM's schedulers. We have implemented our own scheduler and integrated it into LLVM 2.9 as yet-another scheduler. Our scheduler uses a combinatorial optimization approach to balance ILP and register pressure. In one experiment, we added more precise latency information for

Hi Andrew, What we have is not a patch to any of LLVM's schedulers. We have implemented our own scheduler and integrated it into LLVM 2.9 as yet-another scheduler. Our scheduler uses a combinatorial optimization approach to balance ILP and register pressure. In one experiment, we added more precise latency information for most common x86 instructions to our scheduler and noticed a 10%