search for: pse

Looking at the 2.0 code, it looks like the guest OSs are made to believe that PSE is not available. Is this a design choice? Has any work been done on supporting 4M pages in guest kernels? Regards, K. Y ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real...

...stance class (i.e., [0 ? 2]; ]2 ? 4]; ]4 ? 6]; ]6 ? 8]; ]8 ? 10];??; ]48 ? 50]) >or sample N values from exponential distributions with different rates ? >Here is the code used to perform a LHS when the parameter ?dispersal distance? is defined by one default value in the model: >library(pse) >factors <- c("distance") >q <- c("qexp") >q.arg <- list( list(rate=1/30) ) >uncoupledLHS <- LHS(model=NULL, factors, 50, q, q.arg) >head(uncoupledLHS) >Thanks a lot for your time. >Have a nice day >Nell Nell, I would like to suggest a sli...

Dear List, I am looking for a function `Pseudo standard error' (PSE), which is available in S+ DOX (design of experiemnt) module - Is there a similar function available in R? Reference for PSE function is in the paper: 'Quick and easy analysis of unreplicated factorials' by Russell V. Lenth, Technometrics, 1989, 31, 4, 469-473....

...that's why you don't have POE always-on on a POE enabled switch port.... you can find more info in article area of http://www.poweroverethernet.com and full specs @ http://www.ieee802.org/3/af/index.html You will find a resistance value in the quote below. The value is 19k to 26.5k for PSE detection signature, with a mid value of 22.75K <quote> The Discovery Process Power Over Ethernet PSEs are responsible for ensuring that conventional Ethernet equipment is not damaged by the unexpected application of 48 Volts. The PSEs must determine that a Power Over Ethernet compliant dev...

Hi: Please can somebody explain what this means? It seems to me that this message is new since cvs-010703 (first contributions after wine-20010629.tar.gz) At least I never saw it before. trace:dll:NE_InitDLL Calling LibMain, cs:ip=1147:05dc ds=114f di=114e cx=1000 trace:dll:fill_init_list (C:\WTLIB_X\FMDROP1.VBX) - START trace:dll:fill_init_list (KRNL386.EXE) - START trace:dll:fill_init_list

...: QEMU Virtual CPU version 0.9.1 stepping : 3 cpu MHz : 0.000 cache size : 32 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 4 wp : yes flags : fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx lm up pni bogomips : 1437.69 clflush size : 64 power management: The CPU Mhz is 0 !!!! On dom0 (CentOS 5.5), the "cat /proc/cpuinfo" got: processor : 0 vendor_id : Genui...

> -------- Original message -------- > Subject: Re: [libvirt-users] Can I configure cores instead of CPU's > From: Todd And Margo Chester <toddandmargo at gmail.com> > To: "libvirt-users at redhat.com" <libvirt-users at redhat.com> > CC: > > > Hi All, > > Scientific Linux 6.1 x64 > qemu-kvm-0.12.1.2-2.160.el6_1.2.x86_64 > > My XP-Pro

On 2/18/2019 4:15 AM, Michael Platings via llvm-dev wrote: > Taking my previous example [1]: > > InnerLoopVectorizer LB(L, PSE, LI, DT, TLI, TTI, AC, ORE, VF.Width, IC, > &LVL, &CM); > > If we imagine that over time it evolves such that 50% of the variables have been renamed to camelBack versions of the type names, then it will look like this: > > InnerLoopVectorizer LB(loop, PSE, loopInfo, DT,...

Chris Webb <chris at arachsys.com> wrote: > My CPU flags inside the crashing guest look like this: > > fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush > mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl > extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave > avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a mis...

Chris Webb <chris at arachsys.com> wrote: > My CPU flags inside the crashing guest look like this: > > fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush > mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl > extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave > avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a mis...

...esultet in a "Sandy Bridge" model. What I noticed is that for example the "aes" extension is not available in the guest even though it is available on the host cpu. This is what the host cpu looks like: model name : Intel(R) Xeon(R) CPU E5-2650 v3 @ 2.30GHz flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 fma cx16 xtpr pd...

...lity distributions? In particular, how can I use your code to apply my model to each of the 50 rows of the data frame ?tabLHS?? Given that one row corresponds to one model simulation, I should have a value generated by the LHS for all distance classes at the first line of the data frame. library(pse) q <- list("qexp", "qunif", "qunif") q.arg <- list(list(rate=exponential_rate), list(min=0, max=1), list(min=0, max=1)) uncoupledLHS <- LHS(model=model_function, input_parameters, N, q, q.arg) hist(uncoupledLHS$data$dispersal_distance, breaks=10) tabLHS <-...

...x) I can stop this crash by disabling CONFIG_PARAVIRT_SPINLOCKS in my guest kernel, running with -cpu qemu64 instead of -cpu host, or running with -smp 1 instead of -smp 4. (Removing/changing the -machine q35 makes no difference.) My CPU flags inside the crashing guest look like this: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse 3dnowp...

...x) I can stop this crash by disabling CONFIG_PARAVIRT_SPINLOCKS in my guest kernel, running with -cpu qemu64 instead of -cpu host, or running with -smp 1 instead of -smp 4. (Removing/changing the -machine q35 makes no difference.) My CPU flags inside the crashing guest look like this: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl extd_apicid pni pclmulqdq ssse3 fma cx16 sse4_1 sse4_2 x2apic popcnt aes xsave avx f16c hypervisor lahf_lm cmp_legacy svm cr8_legacy abm sse4a misalignsse 3dnowp...

...ily : 6 model : 60 model name : Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz stepping : 3 microcode : 0x7 cpu MHz : 800.000 cache size : 8192 KB physical id : 0 siblings : 8 core id : 0 cpu cores : 4 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 fma cx16 xtpr pd...

On Mon, 11 Feb 2019 at 23:20, Philip Reames via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I don't care about the convention, but I'm really not sure it's worth the churn which would result in the code base. The hurtle which needs cleared here is not "is it a better naming style", but "is the disruption implied by changing to the new convention

Hi gang! At work I have a DL320 G2 machine I use as my desktop (I know, weird!...). Back when I ran RHEL WS 2.1 on it, it always ran a SMP kernel because it has a HypterThread capable processor. When I installed (fresh from scratch) Centos 4.4 on it a while back, though, Centos installed only the UP kernel. I've looked in the BIOS for settings to enable/disable HT support and I don't

...; stepping : 3 > microcode : 0x7 > cpu MHz : 800.000 > cache size : 8192 KB > physical id : 0 > siblings : 8 > core id : 3 > cpu cores : 4 > apicid : 7 > initial apicid : 7 > fpu : yes > fpu_exception : yes > cpuid level : 13 > wp : yes > flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat > pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb > rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology > nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx > est tm2 ss...

...y such a utility? Otherwise, is there a way without loops? Thanks as always Anne ---------------------------------------------------- Anne Piotet Tel: +41 79 359 83 32 (mobile) Email: anne.piotet@m-td.com --------------------------------------------------- M-TD Modelling and Technology Development PSE-C CH-1015 Lausanne Switzerland Tel: +41 21 693 83 98 Fax: +41 21 646 41 33 -------------------------------------------------- [[alternative HTML version deleted]]

...shkernel=auto rhgb quiet intel_iommu=on And supported according dmesg output: root at lapdev01# dmesg | grep IOM [ 0.000000] Intel-IOMMU: enabled As you can see in the following output, VT-d extensions are supported also: root at lapdev01:~# cat /proc/cpuinfo | grep vmx flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 fma cx16 xtpr pdcm p...