Displaying 9 results from an estimated 9 matches for "processormodel".
2020 Sep 23
2
Incorrect Cortex-R4/R4F/R5 ProcessorModel in ARM.td
In ARM.td, I see that the ProcessorModel for cortex-r4, cortex-r4f, and cortex-r5 (as well as r7 and r8) is based on "CortexA8Model", which seems incorrect. When this was added in 2015, there were also comments associated with this configuration, such as "// FIXME: R5 has currently the same ProcessorModel as A8" (late...
2015 Oct 15
3
what can cause a "CPU table is not sorted" assertion
...ltiple ports.
def SlotAny : ProcResGroup<[Slot0, Slot1]>;
def : WriteRes<WriteALU, [SlotAny]> {
let Latency = 1;
let ResourceCycles =[1];
}
def : WriteRes<WriteBranch, [Slot0]> {
let Latency = 1;
let ResourceCycles =[1];
}
}
I've also changed OR1K.td to have
def : ProcessorModel<"generic", MyTargetModel, [FeatureDiv, FeatureMul]>;
def : ProcessorModel<"or1200", MyTargetModel, [FeatureDiv, FeatureMul]>;
No issues compiling the code. But when I run the following command I get
and assertion:
llc -mcpu=mytarget hello_world.compiled.ll -debug...
2016 Feb 24
2
Performance degradation on ARMv7 (cortex-a9)
...s per ARM architecture.//
// This allows for accurate architecture targeting as well as removing//
// duplicate information (hardcoded feature strings) from MCTargetDesc./
I see that in lib/Target/ARM/ARM.td all the features have been removed
from Proc definition (e.g.: ProcA9) and added to ProcessorModel
definition (e.g.: ProcessorModel<"cortex-a9").
But I find that the features from Proc are still being read and set in
MCSubtargetInfo through the ARMFeatureKV table. So if the Proc is empty
the corresponding feature is not being set.
In my case, if I add FeatureFP16 back to the Proc...
2016 Feb 24
1
Performance degradation on ARMv7 (cortex-a9)
...ecture.
> This allows for accurate architecture targeting as well as removing
> duplicate information (hardcoded feature strings) from MCTargetDesc./
>
> I see that in lib/Target/ARM/ARM.td all the features have been removed
> from Proc definition (e.g.: ProcA9) and added to ProcessorModel
> definition (e.g.: ProcessorModel<"cortex-a9").
> But I find that the features from Proc are still being read and set in
> MCSubtargetInfo through the ARMFeatureKV table. So if the Proc is
> empty the corresponding feature is not being set.
> In my case, if I add Fea...
2016 Mar 05
2
Enable / Disable a processor feature
...==----------------------------------------------------------------------===//
// Esencia processors supported.
//===----------------------------------------------------------------------===//
class Proc<string Name, SchedMachineModel Model,
list<SubtargetFeature> Features>
: ProcessorModel<Name, Model, Features>;
def : Proc<"esencia", EsenciaModel, [FeatureMul,
FeatureDiv,
FeatureCmov,
FeatureAddc
]>;
This is what I...
2017 Oct 17
2
getCacheSize() / subtarget machine id
...k what the ideas are on how this should be done best.
Some thoughts:
* Just comparing the CPU string during initializaition is possible (and
perhaps simple and good enough), but ideally it would be better not to
do this, as those strings are already in the (SystemZ)Processors.td file.
* Extend ProcessorModel with a "processor model ID" that the subtarget
could later retrieve?
* Extend MCSchedModel instead? Or even extend MCSchedModel with the
cache size / associativity directly for this case?
My first thought was to just have an enum in the target and then check
the CPU string (per the f...
2016 Dec 16
1
help/hints/suggestions/tips please: how to give _generic_ compilation for a particular ISA a non-zero LoopMicroOpBufferSize?
...MCSchedModel::DefaultIssueWidth,
MCSchedModel::DefaultMicroOpBufferSize,
MCSchedModel::DefaultLoopMicroOpBufferSize,
... where "NoSchedModel" seems to be generated from this TableGen code in the source-tree file
at "llvm/lib/Target/AArch64/AArch64.td":
def : ProcessorModel<"generic", NoSchedModel, [
FeatureCRC,
FeatureFPARMv8,
FeatureNEON,
FeaturePerfMon,
FeaturePostRAScheduler
]>;
... wherein it`s obvious how to add som...
2015 Oct 21
2
bad identification of the CPU pentium dual core ( penryn instead of core2 )
lvm 3.7.0 treats pentium dual core ( cpu family 6 model 23 ) as "penryn"
cpu, which triggers a serious bug :
- crashs in openGL programs when llvm is used by mesa package, llvm will
produces binary code with SSE4 instructions, which is not compatible
with pentium dual core, because this CPU doesn't support SSE4
instructions ( bad cpu opcodes ),
with llvm 3.6.2 this bug doesn't
2015 Sep 15
3
The Trouble with Triples
On 15 September 2015 at 19:34, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote:
> We can go further with this analogy too. For example, let's say John Smith
> with the SSN Y also answers to the name Rameses. This is the problem that
> Renato is working on. Renato needs to be able to see the name Rameses and
> map this to the correct John Smith (or at least someone very