Barto via llvm-dev
2015-Oct-21 19:23 UTC
[llvm-dev] bad identification of the CPU pentium dual core ( penryn instead of core2 )
lvm 3.7.0 treats pentium dual core ( cpu family 6 model 23 ) as
"penryn"
cpu, which triggers a serious bug :
- crashs in openGL programs when llvm is used by mesa package, llvm will
produces binary code with SSE4 instructions, which is not compatible
with pentium dual core, because this CPU doesn't support SSE4
instructions ( bad cpu opcodes ),
with llvm 3.6.2 this bug doesn't occur because pentium dual core was
treated as "core2" cpu, which is the good behaviour,
the llvm git commit who has introduced this bug is :
cd83d5b5071f072882ad06cc4b904b2d27d1e54a
https://github.com/llvm-mirror/llvm/commit/cd83d5b5071f072882ad06cc4b904b2d27d1e54a
this faulty commit has deleted a crucial test about SSE4 for CPU family
6 model 23 :
return HasSSE41 ? "penryn" : "core2";
the solution is simply to re-add this test for CPU family 6 model 23,
here is the patch :
--- a/lib/Support/Host.cpp 2015-10-14 07:13:52.381374679 +0200
+++ b/lib/Support/Host.cpp 2015-10-14 07:13:28.224708323 +0200
@@ -332,6 +332,8 @@
// 17h. All processors are manufactured using the 45 nm process.
//
// 45nm: Penryn , Wolfdale, Yorkfield (XE)
+ // Not all Penryn processors support SSE 4.1 (such as the Pentium
brand)
+ return HasSSE41 ? "penryn" : "core2";
case 29: // Intel Xeon processor MP. All processors are manufactured
using
// the 45 nm process.
return "penryn";
Craig Topper via llvm-dev
2015-Oct-21 20:43 UTC
[llvm-dev] bad identification of the CPU pentium dual core ( penryn instead of core2 )
That check should not be needed because getHostCPUFeatures() should also be called and detect that SSE41 is not supported. This should then pass "-sse41" into the feature selection. On Wed, Oct 21, 2015 at 2:23 PM, Barto via llvm-dev <llvm-dev at lists.llvm.org> wrote:> lvm 3.7.0 treats pentium dual core ( cpu family 6 model 23 ) as "penryn" > cpu, which triggers a serious bug : > > - crashs in openGL programs when llvm is used by mesa package, llvm will > produces binary code with SSE4 instructions, which is not compatible > with pentium dual core, because this CPU doesn't support SSE4 > instructions ( bad cpu opcodes ), > > with llvm 3.6.2 this bug doesn't occur because pentium dual core was > treated as "core2" cpu, which is the good behaviour, > > the llvm git commit who has introduced this bug is : > > cd83d5b5071f072882ad06cc4b904b2d27d1e54a > > > https://github.com/llvm-mirror/llvm/commit/cd83d5b5071f072882ad06cc4b904b2d27d1e54a > > this faulty commit has deleted a crucial test about SSE4 for CPU family > 6 model 23 : > > return HasSSE41 ? "penryn" : "core2"; > > the solution is simply to re-add this test for CPU family 6 model 23, > here is the patch : > > --- a/lib/Support/Host.cpp 2015-10-14 07:13:52.381374679 +0200 > +++ b/lib/Support/Host.cpp 2015-10-14 07:13:28.224708323 +0200 > @@ -332,6 +332,8 @@ > // 17h. All processors are manufactured using the 45 nm > process. > // > // 45nm: Penryn , Wolfdale, Yorkfield (XE) > + // Not all Penryn processors support SSE 4.1 (such as the Pentium > brand) > + return HasSSE41 ? "penryn" : "core2"; > case 29: // Intel Xeon processor MP. All processors are > manufactured using > // the 45 nm process. > return "penryn"; > > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-- ~Craig -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20151021/281713c6/attachment.html>
Barto via llvm-dev
2015-Oct-21 21:06 UTC
[llvm-dev] bad identification of the CPU pentium dual core ( penryn instead of core2 )
the problem is that mesa developpers don't use this function
"getHostCPUFeatures()" in their source code,
I don't know the details of llvm 3.7.0, but if I check the file
/lib/Target/X86.td I can see a list of CPU names, the same list used by
/lib/Support/Host.cpp,
in /lib/Target/X86.td there are a sort of definitions of features for
each CPU :
/ Intel Core 2 Solo/Duo.
def : ProcessorModel<"core2", SandyBridgeModel,
[FeatureSSSE3, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
def : ProcessorModel<"penryn", SandyBridgeModel,
[FeatureSSE41, FeatureCMPXCHG16B, FeatureSlowBTMem]>;
the problem I see here is that "penryn" processor in llvm source code
has the feature "SSE41", a default behaviour in llvm who can explain
this bug if "pentium dual core" are treated as "penryn"
instead of
"core2", don't forget that "pentium dual core" ( cpu
family 6 model 23 )
don't support SSE41,
I don't understand the purpose of the /lib/Target/X86.td file, is it a
kind of default behaviour for llvm when he produces binary code ?
there is something weird about your commit
cd83d5b5071f072882ad06cc4b904b2d27d1e54a, with some archlinux
developpers we don't understand why you have deleted the test about
SSE41 for CPU family 6 model 23, the subject of your commit is "AVX"
not
"SSE41", the question has been asked to you in this bug report :
https://llvm.org/bugs/show_bug.cgi?id=25021#c7
what is clear is that llvm 3.6.3 doesn't have the bug and people who
have a pentium dual core will meet serious bug with mesa ( if mesa is
linked to llvm 3.7.0 )
Le 21/10/2015 22:43, Craig Topper a écrit :> That check should not be needed because getHostCPUFeatures() should also
> be called and detect that SSE41 is not supported. This should then pass
> "-sse41" into the feature selection.
>
> On Wed, Oct 21, 2015 at 2:23 PM, Barto via llvm-dev
> <llvm-dev at lists.llvm.org <mailto:llvm-dev at
lists.llvm.org>> wrote:
>
> lvm 3.7.0 treats pentium dual core ( cpu family 6 model 23 ) as
"penryn"
> cpu, which triggers a serious bug :
>
> - crashs in openGL programs when llvm is used by mesa package, llvm
will
> produces binary code with SSE4 instructions, which is not compatible
> with pentium dual core, because this CPU doesn't support SSE4
> instructions ( bad cpu opcodes ),
>
> with llvm 3.6.2 this bug doesn't occur because pentium dual core
was
> treated as "core2" cpu, which is the good behaviour,
>
> the llvm git commit who has introduced this bug is :
>
> cd83d5b5071f072882ad06cc4b904b2d27d1e54a
>
>
https://github.com/llvm-mirror/llvm/commit/cd83d5b5071f072882ad06cc4b904b2d27d1e54a
>
> this faulty commit has deleted a crucial test about SSE4 for CPU family
> 6 model 23 :
>
> return HasSSE41 ? "penryn" : "core2";
>
> the solution is simply to re-add this test for CPU family 6 model 23,
> here is the patch :
>
> --- a/lib/Support/Host.cpp 2015-10-14 07:13:52.381374679 +0200
> +++ b/lib/Support/Host.cpp 2015-10-14 07:13:28.224708323 +0200
> @@ -332,6 +332,8 @@
> // 17h. All processors are manufactured using the 45
> nm process.
> //
> // 45nm: Penryn , Wolfdale, Yorkfield (XE)
> + // Not all Penryn processors support SSE 4.1 (such as the
> Pentium brand)
> + return HasSSE41 ? "penryn" : "core2";
> case 29: // Intel Xeon processor MP. All processors are
> manufactured using
> // the 45 nm process.
> return "penryn";
>
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
>
>
> --
> ~Craig