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What does MIOperandInfo exactly mean while defining an Operand class? e.g. here class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm); } -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20071204/23db1ace/attachment.html>

Hi, After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like: // A list of registers separated by comma. Used by load/store multiple. def reglist : Operand<i32> { let PrintMethod = "printRegisterList"; } def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), IndexModeNone, LdStMulFrm, IIC_iLoadm, "ldm${addr:submode}${p}\t$addr, $dsts", "", []>; Ta...

...lesen wrote: > Hi, > > After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like: > > // A list of registers separated by comma. Used by load/store multiple. > def reglist : Operand<i32> { > let PrintMethod = "printRegisterList"; > } > > def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, > reglist:$dsts, variable_ops), > IndexModeNone, LdStMulFrm, IIC_iLoadm, > "ldm${addr:submode}${p}\t$addr, $dsts"...

Hi, That's what the DecoderMethod is for. Similarly ParserMatchClass for the asm parser and PrintMethod for the asm printer: def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; } def pred : PredicateOperand<OtherVT, (ops i32imm, i32imm), (ops (i32 14), (i32 zero_reg))> { let PrintMethod = "printPredicateOperand"; let Parse...

I see. If I put simm16 and immSExt16x in place of uimm16 and immZExt16x respectively, the imm matches but it prints out -32768 (which is invalid for sub16u). We are using uimm16 not match unsigned but for PrintMethod, effectively uimm16 and simm16 are both Operand<i16>. I'm still unclear why simm16 matches and uimm16 does not. Here is the pattern if that helps at all. So just as a reference: def simm16 : Operand<i16> { let DecoderMethod= "DecodeSimm16"; let OperandType = &qu...

...>> >> After Bob fixed the two-address format of the ARM ldm/stm instructions, a problem remains. The load multiple instruction looks like: >> >> // A list of registers separated by comma. Used by load/store multiple. >> def reglist : Operand<i32> { >> let PrintMethod = "printRegisterList"; >> } >> >> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, >> reglist:$dsts, variable_ops), >> IndexModeNone, LdStMulFrm, IIC_iLoadm, >> "ldm${addr:submode}${p...

...otherwise we get the difficult error: <<In LD_INDIRECT_D2: Type inference contradiction found, 'v128i16' needs to be scalar>>), like in the following complete specification: // Inspired heavily from lib/Target/X86/X86InstrInfo.td class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops i8imm, i32imm); let OperandType = "OPERAND_MEMORY"; } // Gather mem operands class X86VMemOperand<RegisterClass RC, string printMethod>...

...let Inst{31-24} = offset{7-0}; let Inst{23-16} = offset{15-8}; let Inst{15} = 0b1; let Inst{14-13} = 0b00; let Inst{12-8} = 0b01101; let Inst{7-0} = opcode; } and I have def pcoffset8 : Operand<i8>, ImmLeaf<i8, [{ return Immediate >= -128 && Immediate <= 127; }]> { let PrintMethod = "printPCRelImmOperand"; let MIOperandInfo = (ops i8imm); let ParserMatchClass = ImmediateAsmOperand<"Imm8">; let EncoderMethod = "getMemOpValue"; let DecoderMethod = "DecodeMemOperand"; } def pcoffset16 : Operand<i16>, ImmLeaf<i16, [...

...3 at gmail.com> > wrote: > >> I see. If I put simm16 and immSExt16x in place of uimm16 and >> immZExt16x >> respectively, the imm matches but it prints out -32768 (which is >> invalid >> for sub16u). We are using uimm16 not match unsigned but for >> PrintMethod, >> effectively uimm16 and simm16 are both Operand<i16>. I'm still unclear >> why >> simm16 matches and uimm16 does not. Here is the pattern if that helps >> at >> all. >> >> So just as a reference: >> >> def simm16 : Operand&...

...the > difficult error: <<In LD_INDIRECT_D2: Type inference contradiction found, 'v128i16' needs > to be scalar>>), like in the following complete specification: > // Inspired heavily from lib/Target/X86/X86InstrInfo.td > class X86MemOperand<string printMethod> : Operand<iPTR> { > let PrintMethod = printMethod; > let MIOperandInfo = (ops i8imm, i32imm); > let OperandType = "OPERAND_MEMORY"; > } > // Gather mem operands > class X86VMemOperand<RegisterClass RC, st...

...I understand that input operand list i.e. ins of stwu should get matched with the given pre_store. But I am confused as to how "ptroff" and "ptrreg" get matched with "memri" used in STWU? For reference[1] memri is defined as: def memri :Operand<iPTR> { let PrintMethod = "printMemRegImm"; let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); let EncoderMethod = "getMemRIEncoding";} [1] https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?view=markup -- * Anitha* -------------- next part -------------- An H...

Hello. Will, thanks a lot for pointing me to the MaskedGatherSDNode and mgatherv4i32. I have to say that the definition of the "multiclass avx512_gather" from lib/Target/X86/X86InstrAVX512.td is difficult to follow and I prefer not to use it. I currently have some serious problems with TableGen - it gives an assertion failure:

...ef> = LDRD %reg1030, %reg0, 264, pred:14, pred:%reg0; mem:LD4[%uglygep10], mem:LD4[%uglygep2021] If I had to guess, I would think it's because of how LDR is defined: def addrmodepc : Operand<i32>, ComplexPattern<i32, 2, "SelectAddrModePC", []> { let PrintMethod = "printAddrModePCOperand"; let MIOperandInfo = (ops GPR, i32imm); } def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr, "ldr", "\t$dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; It's using ad...

On Tue, Jun 24, 2014 at 4:03 PM, Tim Northover <t.p.northover at gmail.com> wrote: > Hi Jun, > > On 24 June 2014 08:08, Jun Koi <junkoi2004 at gmail.com> wrote: > > def LEA16r : I<0x8D, MRMSrcMem, > > (outs GR16:$dst), (ins i32mem:$src), > > "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, > >

I'm trying to write a store pattern that accepts both i32 and f32, however, when tablegen generates the code, it only generates the code for i32 only. def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; def MEM : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR, GPR); } def global_st : SDNode<"AMDILISD::GLOBAL_STORE", SDTStore, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def global_store : PatFrag<(ops node:$val, node:$ptr), (st node:$val, node:$ptr), [...

...A single 32-bit immediate (i32) encodes how to add many MachineOperands to the MachineInstr object (With the help of functions in X86InstrBuilder.h). // similar to X86MemOperand in X86InstrInfo.td !! class ManyOperands : Operand<i32> { let NumMIOperands = 100; // a very large number let PrintMethod = "printManyOperands"; } def MO : ManyOperands; def FOOBAR: Instruction<(ops MO:$operands), "foobar {$operands}">; (2) 'Collapse' all operands in .td file. Contrary to method (1), each operand is explicitly specified. def FOOBAR: Instruction<(ops R32:$src0, R...

...#39;t know what xform would operate on. With immediates you have a DAG node you can generate. Also, it does seem like this is a folding operation PerformDAGCombine() could do but that approach seems like it needs to modify the registerclass, or something similar, that would eventually get you to a PrintMethod that could insert the dash/negate in front of the operand. I didn't want to define a 'mirror' registerclass for my existing register set that would just have the Name as the negated version. That would have its own complications. Is there a superior way to do this with DAG combine? Tha...

...ne of the fixed inputs. The following operands are fine as they fall in the variable_ops part of the instruction. > > I need a way of referring to the variable_ops by name without forcing the first operand to be an input. Ok. >>> def reglist : Operand<i32> { >>> let PrintMethod = "printRegisterList"; >>> let MIOperandInfo = (ops variable_ops); >>> } >>> >>> def LDM : AXI4ld<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts), > > This syntax is not ideal, because reglist:$dsts is a variable list of output operands...

I have two questions regarding MachineMemOperands and dependence information. Q1) I noticed that MachineMemOperands are lost when two LDRs are combined and a LDRD is generated in ARMPreAllocLoadStoreOpt:::RescheduleOps. (before optimization) %reg1033<def> = LDR %reg1030, %reg0, 4100, pred:14, pred:%reg0; mem:LD4[%uglygep10] %reg1054<def> = LDR %reg1030, %reg0, 4104, pred:14,

...ins of stwu should get > matched with the given pre_store. But I am confused as to how > "ptroff" and "ptrreg" get matched with "memri" used in STWU? > > > For reference[1] memri is defined as: > > def memri :Operand<iPTR> { > > let PrintMethod = "printMemRegImm"; > > let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); > > let EncoderMethod = "getMemRIEncoding"; > > } > > [1] > https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?view=markup > -- >...