search for: prefetchnta

Dear All, I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>" instruction to x86_64 code. The code for adding the 32-bit instruction is: BuildMI(MBB,MI,dl,TII->get(X86::PREFETCHNTA)).addReg(0).addImm(0).addReg(0...

On 9/11/12 12:10 PM, Stephen Checkoway wrote: > On Sep 11, 2012, at 10:57 AM, John Criswell wrote: > >> I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>" instruction to x86_64 code. > Given that you don't actually want to execute this instruction ever, is there a reason to even emit the instruction? I...

On Sep 11, 2012, at 10:57 AM, John Criswell wrote: > I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>" instruction to x86_64 code. Given that you don't actually want to execute this instruction ever, is there a reason to even emit the instruction? Why no...

...ws a packet with the NdisPacketTcpChecksumSucceeded flag set. The problem is that the machine locks hard. After some tedious work with the debugger, I have found that Windows makes a call to a routine called RtlPrefetchMemoryNonTemporal, which looks like this: 8088e579 mov eax,dword ptr [nt!KePrefetchNTAGranularity 8088e57e 0f184100 prefetchnta [ecx] 8088e582 add ecx,eax 8088e584 sub edx,eax 8088e586 ja nt!RtlPrefetchMemoryNonTemporal+0x6 (8088e57e) 8088e588 ret Unfortunately it appears that the value at nt!KePrefetchNTAGranularity is 0, hence the infinite loop. Is there anything in...

Trying again from the correct email address, sorry if you get this twice. On Sep 11, 2012, at 10:57 AM, John Criswell wrote: > I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>" instruction to x86_64 code. Given that you don't actually want to execute this instruction ever, is there a reason to even emit the instruction? Why no...

...riswell Sent: Tuesday, September 11, 2012 1:42 PM To: Steve Checkoway Cc: LLVMdev at cs.uiuc.edu Subject: Re: [LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass ... > >> The code for adding the 32-bit instruction is: >> >> BuildMI(MBB,MI,dl,TII->get(X86::PREFETCHNTA)).addReg(0).addImm(0).add >> Reg(0).addImm(<constant>).addReg(0); > That's surprising to me. What are all of those registers and immediates for? That is precisely my question. What do all of those register and immediate arguments do? -- John T. The X86 backend records a machi...

..., i32 1) tail call void @llvm.prefetch(i8* %6, i32 1, i32 2, i32 1) tail call void @llvm.prefetch(i8* %7, i32 1, i32 3, i32 1) The generated x86_64 code for the first 4 calls, where the read/write parameter is 0 (read) is exactly as expected: (Generated with clang -O2 -S -march=btver2 test.c) prefetchnta foo(%rip) prefetcht2 foo(%rip) prefetcht1 foo(%rip) prefetcht0 foo(%rip) The question is what should be expected when the r/w parameter is 1 (write). Currently the backend generates: prefetchnta foo(%rip) prefetcht2 foo(%rip) prefetcht1 foo(%rip) prefetchw foo(%rip) However, a different...

Hi, I am new to LLVM and am trying to modify clang for some work. I tried to insert an instruction: prefetchnta $100 at the beginning of a function. I encountered a problem when I tried to debug it with gdb. There was an assertion failure and printed some information without stack trace. The process has been finished when it printed the information. I tried to set a breakpoint at the operator[] with: bre...