Displaying 20 results from an estimated 2614 matches for "prefetcheable".
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prefetchable
2014 Sep 23
2
[LLVMdev] Use of llvm.prefetch intrinsic for basicblock prefetching
Hi,
Thanks,
I am targetting x86 architecture.
-Usha
On Mon, Sep 22, 2014 at 10:39 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> ----- Original Message -----
> > From: "usha shau" <ushashau1 at gmail.com>
> > To: llvmdev at cs.uiuc.edu
> > Sent: Monday, September 22, 2014 7:01:20 AM
> > Subject: [LLVMdev] Use of llvm.prefetch intrinsic for
2014 Sep 22
2
[LLVMdev] Use of llvm.prefetch intrinsic for basicblock prefetching
Hi,
I am new to LLVM and using it for my project where I want to perform
software prefetching of code blocks.
I am not able to use the llvm.prefetch instruction to fetch a block of code
in instruction cache. The LangRef
<http://llvm.org/docs/LangRef.html#llvm-prefetch-intrinsic>manual mentions
that giving last argument as '0' performs prefetch on instruction cache.
However, I get
2019 Oct 18
3
Dovecot v2.3.8 released
On 2019-10-18 13:25, Tom Sommer via dovecot wrote:
> I am seeing a lot of errors since the upgrade, on multiple client
> accounts:
>
> Info: Connection closed: read(size=7902) failed: Connection reset by
> peer (UID FETCH running for 0.242 + waiting input/output for 108.816
> secs, 60 B in + 24780576+8192 B out, state=wait-output)
>
> Using NFS storage (not running with
2019 Oct 08
4
Dovecot v2.3.8 released
https://dovecot.org/releases/2.3/dovecot-2.3.8.tar.gz
https://dovecot.org/releases/2.3/dovecot-2.3.8.tar.gz.sig
Binary packages in https://repo.dovecot.org/
Changes
+ Added mail_delivery_started and mail_delivery_finished events, see
https://doc.dovecot.org/admin_manual/list_of_events/ for details.
+ dsync-replication: Don't replicate users who have "noreplicate" extra
field in
2019 Oct 08
4
Dovecot v2.3.8 released
https://dovecot.org/releases/2.3/dovecot-2.3.8.tar.gz
https://dovecot.org/releases/2.3/dovecot-2.3.8.tar.gz.sig
Binary packages in https://repo.dovecot.org/
Changes
+ Added mail_delivery_started and mail_delivery_finished events, see
https://doc.dovecot.org/admin_manual/list_of_events/ for details.
+ dsync-replication: Don't replicate users who have "noreplicate" extra
field in
2012 Dec 13
2
[LLVMdev] Instruction Prefetching in llvm
HI,
Has anyone ever implemented instruction prefetching with llvm? If so, on
which architectures?
--
Thanks,
Aasheesh
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2015 Jul 30
0
[LLVMdev] [x86] Prefetch intrinsics and prefetchw
Hi,
I am looking at how the PREFETCHW instruction is matched to the IR prefetch intrinsic (and __builtin_prefetch).
Consider this C program:
char foo[100];
int bar(void) {
__builtin_prefetch(foo, 0, 0);
__builtin_prefetch(foo, 0, 1);
__builtin_prefetch(foo, 0, 2);
__builtin_prefetch(foo, 0, 3);
__builtin_prefetch(foo, 1, 0);
__builtin_prefetch(foo, 1, 1);
2013 Apr 10
2
[LLVMdev] How to call the llvm.prefetch intrinsic ?
Hello,
Can anyone please guide me how can I replace a load instruction with a prefetch. I was looking at the intrinsic creation methods of the IRBuilder, but I can only find functions corresponding to memset, memcpy and memmove intrinsics, not for prefetching.
Also, I target x86-64 architectures. Is it sufficient to insert a call to the intrinsic in the LLVM IR to have the corresponding prefetch
2018 Nov 07
3
RFC: System (cache, etc.) model for LLVM
Am Mo., 5. Nov. 2018 um 10:26 Uhr schrieb David Greene <dag at cray.com>:
> Yes, I agree the terminology is confusing. I used the term "stream" in
> the sense of stream processing (https://en.wikipedia.org/wiki/Stream_processing).
> The programming model is very different, of course, but the idea of a
> stream of data that is acted upon and then essentially discarded
2007 Mar 30
3
prefetch + static + deliver
Hi all...
The prefetch entry in the wiki says:
"If you're using Dovecot's local delivery agent, you'll still need a
valid userdb which it can use to locate the users. You can do this by
adding a normal sql/ldap userdb after userdb prefetch."
(http://wiki.dovecot.org/UserDatabase/Prefetch)
My question is:
Does it need to be a SQL/LDAP userdb? How about static or passwd?
2012 Dec 13
0
[LLVMdev] Instruction Prefetching in llvm
On Wed, Dec 12, 2012 at 07:09:45PM -0500, aasheesh kolli wrote:
> HI,
>
> Has anyone ever implemented instruction prefetching with llvm? If so, on which
> architectures?
Grep prefetch in lib/Target/* will show you ARM, X86, and PPC seems
have implemented prefetch instruction. LLVM provides prefetch intrinsic
[1] so that you can insert it in LLVM IR as a hint to code generator.
I
2014 Dec 06
3
userdb lookup not possible with only userdb prefetch
Hello,
I am setting up a new server and migrating my Dovecot 1.2.9 config to
the new 2.2.9 version. There wasn't much to keep from the old version so
I had to recreate the config from scratch. Now I think I'm done but I
can't login to IMAP. The log says this:
> dovecot: auth: Error: prefetch(box@****.de,2001:****:7765,<bzAOP5QJXwAgAQpgEAXJAZyOMB1qBXdl>): userdb lookup not
2012 Mar 02
2
[LLVMdev] Adjusting Load Latencies
Hello,
I am interested in writing an analysis pass that looks at the stride
used for loads in a loop and passes that information down so that it
can be used by the instruction scheduler. The reason is that if the
load stride is greater than the cache line size, then I would expect
the load to always miss the cache, and, as a result, the scheduler
should use a much larger effective latency when
2013 Apr 10
0
[LLVMdev] How to call the llvm.prefetch intrinsic ?
Alexandra,
I'm not sure what you mean by "replace", but I have code that does this to insert prefetches:
Type *I8Ptr = Type::getInt8PtrTy((*I)->getContext(), PtrAddrSpace);
Value *PrefPtrValue = ...
IRBuilder<> Builder(MemI);
Module *M = (*I)->getParent()->getParent();
Type *I32 = Type::getInt32Ty((*I)->getContext());
Value
2012 Mar 02
0
[LLVMdev] Adjusting Load Latencies
On Mar 2, 2012, at 9:01 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> Hello,
>
> I am interested in writing an analysis pass that looks at the stride
> used for loads in a loop and passes that information down so that it
> can be used by the instruction scheduler. The reason is that if the
> load stride is greater than the cache line size, then I would expect
> the load
2010 Mar 02
2
crash when using the cp command to copy files off a striped gluster dir but not when using rsync
Hi,
I've got this strange problem where a striped endpoint will crash when
I try to use cp to copy files off of it but not when I use rsync to
copy files off:
[user at gluster5 user]$ cp -r Python-2.6.4/ ~/tmp/
cp: reading `Python-2.6.4/Lib/lib2to3/tests/data/fixers/myfixes/__init__.py':
Software caused connection abort
cp: closing
2014 Dec 07
1
userdb lookup not possible with only userdb prefetch
Am 07.12.2014 um 00:56 schrieb Alexander Dalloz:
> You did fulfill the requzirements for prefetch to work documented in the
> wiki?
>
> http://wiki2.dovecot.org/UserDatabase/Prefetch
Ehm, this is my SQL configuration 'dovecot-sql.conf.ext':
> driver = mysql
> connect = host=**** user=**** password=**** dbname=****
> default_pass_scheme = PLAIN
> password_query = \
2016 May 28
1
Determination of statements that contain only matrix multiplication
Sorry for not responding earlier.
On 05/20/2016 03:05 PM, Roman Gareev wrote:
> Thank you very much for the advices! I could probably try to avoid
> using of nonhardware prefetching in the project, if Tobias doesn’t
> disagree with it. My understanding is that prefetching isn’t used
> explicitly in [1] and, according to [2], in some cases 90% of the
> turbo boost peak of the
2007 Nov 06
1
IO window: disabled
Hello
We are seeing the following lines in our /var/log/kern file.
and I am wondering why IO window is disabled for those pci bridges
and if it is necessary to enable them.
Nov 1 15:19:18 Song kernel: IO window: disabled.
Nov 1 15:19:18 Song kernel: MEM window: f4000000-f7ffffff
Nov 1 15:19:18 Song kernel: PREFETCH window: disabled.
Nov 1 15:19:18 Song kernel: PCI: Bridge: 0000:07:00.0
Nov
2003 Sep 04
3
Cant locate my X100P
Hello
After having installed my X100P, /proc/pci and /proc/interrupts dosent
locate them.
In my PCI list is it the Communication controller: Tiger Jet Network Inc ?
then is dosent have a IRQ listed in /proc/pci..
All help appreciated
Thanks and Regards
Ajit
===========================/proc/pci==================================
PCI devices found:
Bus 0, device 0, function 0:
Host