Displaying 12 results from an estimated 12 matches for "predicate_unindexedstor".
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predicate_unindexedstore
2009 Dec 02
5
[LLVMdev] Selecting Vector Shuffle of Different Types
...plified for the sake of exposition but this gets the idea across).
TableGen reports a type contradition:
VEXTRACTF128_256mri: (st:isVoid (vector_shuffle:v4f32 (undef:v8f32),
VR256:v8f32:$src1, (build_vector)<<P:Predicate_VEXTRACTF128_shuffle_mask>>:
$src2), addr:iPTR:
$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
tblgen: In VEXTRACTF128_256mri: Type inference contradiction found in node
vector_shuffle!
Well, it's right! So how do I express this kind of thing? Since LLVM 2.5
shufflevector supports creating a vector of...
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
...(bitconvert VRR128:$src)), addr:$dst)],
IIC_MOV_MEM>, TA;
def: Pat<(store (v32f32 (bitconvert (VRR128:$src))), addr:$dst),
(STORE_DWORD addr:$dst, VRR128:$src)>;
but getting the following error;
STORE_DWORD: (st (bitconvert:v32i32 VRR128:{v32i32:v32f32}:$src),
addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
Included from /PIM/lib/Target/X86/X86.td:832:
/lib/Target/X86/X86InstrInfo.td:3166:1: error: In STORE_DWORD: Could not
infer all types in pattern!
def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst,
VRR128:$src),
^
anonymous_4820: /PIM/lib/...
2009 Nov 18
1
[LLVMdev] TableGen Type Contradiction
Can anyone puzzle out what tblgen is trying to tell me here?
VR256:v32i8:$src MD0.VMOVDQA_256mr: (st:isVoid VR256:v32i8:$src, addr:iPTR:
$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
/ptmp/dag/universal_build/debug/DEFAULT/llvm/tblgen: In MD0.VMOVDQA_256mr:
Type inference contradiction found in node!
I don't see any type contradiction.
-Dave
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
...t;
>>
>> def: Pat<(store (v32f32 (bitconvert (VRR128:$src))), addr:$dst),
>> (STORE_DWORD addr:$dst, VRR128:$src)>;
>>
>> but getting the following error;
>> STORE_DWORD: (st (bitconvert:v32i32 VRR128:{v32i32:v32f32}:$src),
>> addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
>> Included from /PIM/lib/Target/X86/X86.td:832:
>> /lib/Target/X86/X86InstrInfo.td:3166:1: error: In STORE_DWORD: Could not
>> infer all types in pattern!
>> def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst,
>&...
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
...(v32f32 (bitconvert (VRR128:$src))), addr:$dst),
>>>> (STORE_DWORD addr:$dst, VRR128:$src)>;
>>>>
>>>> but getting the following error;
>>>> STORE_DWORD: (st (bitconvert:v32i32 VRR128:{v32i32:v32f32}:$src),
>>>> addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
>>>> Included from /PIM/lib/Target/X86/X86.td:832:
>>>> /lib/Target/X86/X86InstrInfo.td:3166:1: error: In STORE_DWORD: Could
>>>> not infer all types in pattern!
>>>> def STORE_DWORD : I<0x70, MRMDestMem, (...
2014 Jun 07
3
[LLVMdev] Load/Store Instruction Error
.../llvm-3.4/lib/Target/XXX/XXXInstrInfo.td:34:1:
error: In LDRAM: Could not infer all types in pattern!
def LDRAM : FG1<0b000001, (outs GPRegs:$dst), (ins mem:$src), "ldram
$dst,$src", [(set GPRegs:$dst, (load addr:$src))]>;
^
STRAM: (st GPRegs:{i32:f32}:$src,
addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>>
Included from
/home/jwon/Desktop/llvmTest/llvm-3.4/lib/Target/XXX/XXXOther.td:10:
Included from /home/jwon/Desktop/llvmTest/llvm-3.4/lib/Target/XXX/XXX.td:1:
/home/jwon/Desktop/llvmTest/llvm-3.4/lib/Target/XXX/XXXInstrInfo.td:36:1:
error: In STRAM: Could no...
2009 Dec 03
0
[LLVMdev] Selecting Vector Shuffle of Different Types
...but this gets the idea across).
>
> TableGen reports a type contradition:
>
> VEXTRACTF128_256mri: (st:isVoid (vector_shuffle:v4f32 (undef:v8f32),
> VR256:v8f32:$src1, (build_vector)<<P:Predicate_VEXTRACTF128_shuffle_mask>>:
> $src2), addr:iPTR:
> $dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>><<P:Predicate_alignedstore>>
> tblgen: In VEXTRACTF128_256mri: Type inference contradiction found in node
> vector_shuffle!
>
> Well, it's right! So how do I express this kind of thing? Since LLVM 2.5
> shufflevector supports...
2020 Jan 09
2
unified register set question
My target machine uses the same 64-bit registers for integers and floating
point. Do I have to specify a different register class for floating point
that uses the same set of registers? Is there a target which does this I can copy?
thanks,
brian
2019 Nov 20
4
Tablegen PAT limitation?
...============
PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedstore>><<P:Predicate_store>>
RESULT: (STOREbos v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)
DAGIselMatcherGen.cpp: 559
Pattern.getSrcPattern()->dump();
// list<dag&a...
2019 Nov 21
2
Tablegen PAT limitation?
...=====
PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedstore>><<P:Predicate_store>>
RESULT: (STOREbos v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)
DAGIselMatcherGen.cpp: 559
Pattern.getSrcPattern()->dump();...
2019 Nov 22
2
Tablegen PAT limitation?
...=====
PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedstore>><<P:Predicate_store>>
RESULT: (STOREbos v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)
DAGIselMatcherGen.cpp: 559
Pattern.getSrcPattern()->dump();...
2019 Nov 25
2
Tablegen PAT limitation?
...=====
PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedstore>><<P:Predicate_store>>
RESULT: (STOREbos v1i16:{ *:[v1i16] }:$rs1, i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)
DAGIselMatcherGen.cpp: 559
Pattern.getSrcPattern()->dump();...