Displaying 15 results from an estimated 15 matches for "predicate_load".
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
...OPC_MoveChild, 0,
> /*2242*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetGlobalAddress),
> /*2245*/ OPC_MoveParent,
> /*2246*/ OPC_MoveParent,
> /*2247*/ OPC_CheckPredicate, 5, // Predicate_unindexedload
> /*2249*/ OPC_CheckPredicate, 6, // Predicate_load
> /*2251*/ OPC_CheckType, MVT::i64,
> /*2253*/ OPC_EmitMergeInputChains1_0,
> /*2254*/ OPC_EmitInteger, MVT::i64, 0,
> /*2257*/ OPC_MorphNodeTo, TARGET_VAL(XSTG::LOADI64_RI),
> 0|OPFL_Chain|OPFL_MemRefs,
> 1/*#VTs*/, MVT::...
2016 Jan 15
2
Expanding a PseudoOp and accessing the DAG
On 1/15/2016 1:08 PM, Phil Tomson wrote:
>
> Ah, I see, the defm is a multi-class so I needed to change it to:
>
> def: Pat<(load (XSTGADDR_NORMAL tglobaladdr:$addr)),
> (LOADI64_RI tglobaladdr:$addr, 0)>;
> // Match load from a relocatable address to a load with GRP:
> def: Pat<(load (XSTGADDR_USE_GRP tglobaladdr:$addr)),
> (LOADI64_RI
2014 Jun 07
3
[LLVMdev] Load/Store Instruction Error
...DD : FG2<0b000000, (outs GPRegs:$dst), (ins GPRegs:$src1,
GPRegs:$src2), "add $dst,$src1,$src2", [(set GPRegs:$dst, (add
GPRegs:$src1, GPRegs:$src2))]>;
Error Message:
LDRAM: (set GPRegs:{i32:f32}:$dst, (ld:{i32:f32}
addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>)
Included from
/home/jwon/Desktop/llvmTest/llvm-3.4/lib/Target/XXX/XXXOther.td:10:
Included from /home/jwon/Desktop/llvmTest/llvm-3.4/lib/Target/XXX/XXX.td:1:
/home/jwon/Desktop/llvmTest/llvm-3.4/lib/Target/XXX/XXXInstrInfo.td:34:1:
error: In LDRAM: Could not infer all types in pattern!
def...
2010 Aug 04
2
[LLVMdev] x86 Vector Shuffle Patterns
...because I'm having some trouble converting some AVX patterns
over to the new system. I'm getting this error from tblgen:
VyPERM2F128PDirrmi: (set:isVoid VR256:v4i64:$dst, (vector_shuffle:v4i64 VR256:v4i64:$src1, (ld:v4i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_vperm2f128>><<X:SHUFFLE_get_vperm2f128_imm>>)
llvm/lib/Target/X86/X86InstrSIMD.td:1705:6: error: In VyPERM2F128PDirrmi: Cannot specify a transform function for a non-input value!
Here the tblgen pattern looks like this:...
2010 Aug 05
0
[LLVMdev] x86 Vector Shuffle Patterns
...m having some trouble converting some AVX patterns
> over to the new system. I'm getting this error from tblgen:
>
> VyPERM2F128PDirrmi: (set:isVoid VR256:v4i64:$dst, (vector_shuffle:v4i64 VR256:v4i64:$src1, (ld:v4i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_vperm2f128>><<X:SHUFFLE_get_vperm2f128_imm>>)
> llvm/lib/Target/X86/X86InstrSIMD.td:1705:6: error: In VyPERM2F128PDirrmi: Cannot specify a transform function for a non-input value!
It turns out this was a tblgen defi...
2009 Jun 17
0
[LLVMdev] help with tablegen
...rouble with the X86 backend where the SSE2 forms of ADD
are defined:
llvm[3]: Building X86.td DAG instruction selector implementation with tblgen
ADDPDrm: (set:isVoid VR128:isFP:$dst, (fadd:isFP
VR128:isFP:$src1, (ld:isFP
addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>))
/home/nicholas/llvm-commit/Debug/bin/tblgen: error:
Included from X86.td:128:
Included from X86InstrInfo.td:3964:
Parsing X86InstrSSE.td:1320: In ADDPDrm: Could not infer all types in
pattern!
defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fa...
2010 Aug 05
1
[LLVMdev] x86 Vector Shuffle Patterns
...trouble converting some AVX patterns
>> over to the new system. I'm getting this error from tblgen:
>>
>> VyPERM2F128PDirrmi: (set:isVoid VR256:v4i64:$dst, (vector_shuffle:v4i64 VR256:v4i64:$src1, (ld:v4i64 addr:iPTR:$src2)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_memop>>)<<P:Predicate_vperm2f128>><<X:SHUFFLE_get_vperm2f128_imm>>)
>> llvm/lib/Target/X86/X86InstrSIMD.td:1705:6: error: In VyPERM2F128PDirrmi: Cannot specify a transform function for a non-input value!
>
> It turns out this was...
2009 Jul 13
0
[LLVMdev] [PATCH] Support asm comment output
On Jul 13, 2009, at 10:02 AM, David Greene wrote:
>>> - Tag instructons with source line information (customers really
>>> want this).
>>
>> Right, that would be nice. This should be synthesizable from the
>> DebugLoc on the instruction in the asm printer, no need to
>> redundantly
>> encode it into the comment field.
>
> Except the DebugLoc
2009 Jul 13
2
[LLVMdev] [PATCH] Support asm comment output
On Monday 13 July 2009 11:40, Chris Lattner wrote:
> > I was attempting to reduce the number of files affected, but if you
> > want this change I'll go ahead and do it.
>
> Makes sense, thanks. Please do it as a separate patch from the other
> changes though since it will be large and mechanical.
Ok, no problem.
> > - Tag instructons with source line information
2009 Jul 13
5
[LLVMdev] [PATCH] Support asm comment output
...LLVM
Instruction: volatile store i32* %ksize, i32** %ksize3 ;
[oox.4 : sln.5]
# [result] Pattern
1367
I then hacked tblgen to output this in the generated isel file:
// Pattern 1367: (ld:i32 addr:iPTR:$src)<<P:Predicate_load>>
// Emits: (MOV32rm:i32 addr:iPTR:$src)
PatternID = 1367;
// Pattern complexity = 19 cost = 1 size = 3
SDValue CPTmp01;
SDValue CPTmp11;
SDValue CPTmp21;
SDValue CPTmp31;
if (SelectAddr(N, N1, CPTmp01, CPTmp11, CPTmp21, CPTmp31)) {
CurDAG->setSubgra...
2016 Jun 22
2
LLVM Backend Issues
Thanks Anton and Krzysztof!
Here is the dump using the -debug flag. At this point I am not making much
sense of this, would it be too much to ask if one of you could walk me
through one of these lines?
One thing that I didn't point out is that I never defined any separate
floating point registers, not sure if this will pose any issue?
Thanks again for your time!
Jeff
jeff at
2019 Nov 20
4
Tablegen PAT limitation?
...} (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedload>><<P:Predicate_load>>
RESULT: (LOADbos:{ *:[v1i16] } i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)
PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } v1i32:{ *:[v1i32] }:$roffset, (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Pr...
2019 Nov 21
2
Tablegen PAT limitation?
...} (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedload>><<P:Predicate_load>>
RESULT: (LOADbos:{ *:[v1i16] } i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)
PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } v1i32:{ *:[v1i32] }:$roffset, (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Pr...
2019 Nov 22
2
Tablegen PAT limitation?
...} (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedload>><<P:Predicate_load>>
RESULT: (LOADbos:{ *:[v1i16] } i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)
PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } v1i32:{ *:[v1i32] }:$roffset, (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Pr...
2019 Nov 25
2
Tablegen PAT limitation?
...} (add:{ *:[v1i32] } (shl:{ *:[v1i32] } (sext:{ *:[v1i32] } v1i16:{ *:[v1i16] }:$roffset), (build_vector:{ *:[v1i32] } (imm:{ *:[i32] })<<P:Predicate_uimm2>>:$rshift)), (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Predicate_unindexedload>><<P:Predicate_load>>
RESULT: (LOADbos:{ *:[v1i16] } i32:{ *:[i32] }:$rbase, v1i16:{ *:[v1i16] }:$roffset, (imm:{ *:[i32] }):$rshift)
PATTERN: (st v1i16:{ *:[v1i16] }:$rs1, (add:{ *:[v1i32] } v1i32:{ *:[v1i32] }:$roffset, (bitconvert:{ *:[v1i32] } i32:{ *:[i32] }:$rbase)))<<P:Pr...