search for: predicate

...from 808 to 3305, then it goes back to 3259 and eventually it matches the wrong instruction. Why did go back from 3305 to 3259? In my XXXGenDAGISel.inc, I can see that the correct instruction is at index 3420 but it never got there. ISEL: Starting pattern match Skipped scope entry (due to false predicate) at index 3, continuing at 808 Skipped scope entry (due to false predicate) at index 809, continuing at 865 Skipped scope entry (due to false predicate) at index 867, continuing at 1091 Skipped scope entry (due to false predicate) at index 1093, continuing at 1578 Skipped scope entry (due t...

Hi, I was wondering if LLVM supports predicates and conditional execution. Something like we have in IA64. There is a register class of predicates and then every instruction may be predicated by a register from this class. For example: cmp_less p, x, y // p is a predicate which gets the result of x < y p add x, x, 2 // if p then do the add...

In our architecture (TCE) we have predicate registers, not flags. But our predicates work in a way that in the predicated instruction do not contain only the predicate register, but a predicate register and boolean value pair, the boolean value stating if the instruction is to be executed only if the register is true(normal behavior of pred...

2011/5/24 Justin Holewinski <justin.holewinski at gmail.com>: > On Tue, May 24, 2011 at 3:02 AM, roy rosen <roy.1rosen at gmail.com> wrote: >> >> Hi, >> >> I was wondering if LLVM supports predicates and conditional execution. >> Something like we have in IA64. >> There is a register class of predicates and then every instruction may >> be predicated by a register from this class. >> For example: >> >> cmp_less p, x, y // p is a predicate which gets the resu...

Hi all, I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this issue) as supported by the OpenIMPACT compiler (=Trimaran). If anyone is interested, I can show some...

...@c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 ISEL: Starting pattern match on root node: t9: ch = store<ST256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 Skipped scope entry (due to false predicate) at index 14, continuing at 81 Skipped scope entry (due to false predicate) at index 82, continuing at 149 Skipped scope entry (due to false predicate) at index 150, continuing at 217 Skipped scope entry (due to false predicate) at index 218, continuing at 267 Skipped scope entry (due to fa...

...gt; >>>> ISEL: Starting pattern match on root node: t9: ch = store<ST256[bitcast >>>> ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, >>>> t11, undef:i64 >>>> >>>> Skipped scope entry (due to false predicate) at index 14, continuing >>>> at 81 >>>> Skipped scope entry (due to false predicate) at index 82, continuing >>>> at 149 >>>> Skipped scope entry (due to false predicate) at index 150, continuing >>>> at 217 >>>> Skipped...

Hi, I am planning to generate code for a peculiar architecture with _no_ branch instructions (!), but with predicated loads and stores to memory. This means the architecture is not Turing complete, is going to waste a lot of computation, and any input program that can hope to get compiled for this architecture must have loops that can be fully unrolled, and all its functions must get fully inlined. Since I have...

...n <roy.1rosen at gmail.com> wrote: > 2011/5/24 Justin Holewinski <justin.holewinski at gmail.com>: > > On Tue, May 24, 2011 at 3:02 AM, roy rosen <roy.1rosen at gmail.com> wrote: > >> > >> Hi, > >> > >> I was wondering if LLVM supports predicates and conditional execution. > >> Something like we have in IA64. > >> There is a register class of predicates and then every instruction may > >> be predicated by a register from this class. > >> For example: > >> > >> cmp_less p, x, y // p is a...

...it. We came up with some ways to do it in LLVM: - Do not add any predication in the IR (except for load and stores through intrinsics), linearize the branches and substitute PHI nodes with selects for merging values . In the backend then we would custom lower the select instruction to produce a predicated mov to choose the right version of the value. I think this option doesn't make use of the possible benefits of the architecture we are targeting at all. - Another way could be adding intrinsics for all instructions in the target to make them support predication, still linearize all the br...

On Wed, Oct 31, 2012 at 09:13:43PM +0100, Bjorn De Sutter wrote: > Hi all, > > I am working on a CGRA backend (something like a 2D VLIW), and we also absolutely need predication. I extended the IfConversion pass to allow it to be executed multiple times and to predicate already predicated code. This is necessary to predicate code with nested conditional statements. At this point, we support or, and, and conditional predicates (see Scott Mahlke's papers on this issue) as supported by the OpenIMPACT compiler (=Trimaran). If anyone is interested, I can show some...

...i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> >>>>>>>>>>>>>> t8, t7, t11, undef:i64 >>>>>>>>>>>>>> >>>>>>>>>>>>>> Skipped scope entry (due to false predicate) at index 14, >>>>>>>>>>>>>> continuing at 81 >>>>>>>>>>>>>> Skipped scope entry (due to false predicate) at index 82, >>>>>>>>>>>>>> continuing at 149 >>>>&gt...

On Tue, May 24, 2011 at 3:02 AM, roy rosen <roy.1rosen at gmail.com> wrote: > Hi, > > I was wondering if LLVM supports predicates and conditional execution. > Something like we have in IA64. > There is a register class of predicates and then every instruction may > be predicated by a register from this class. > For example: > > cmp_less p, x, y // p is a predicate which gets the result of x < y > p ad...

On 22 Oct 2012, at 18:10, <dag at cray.com> wrote: > None of your proposed solutions is ideal. We really should have > first-class predication in the IR. It's only going to get more > important. Perhaps I am missing something, but isn't a predicated instruction effectively an single-instruction version of an arithmetic operation followed by a select? As we can already represent this in the IR, and already match other predicated instructions (e.g. on ARM) to this pattern, what is gained by adding predication directly to the IR? David

Hi, I've done work on predicated SIMD representations for LLVM. If you search through the archives, you may find my "applymask" proposal, which is an attempt at representing predication in a very comprehensive way. I've since stopped pushing the proposal in part because Larrabee's changing fortunes led to a dec...

David Chisnall <David.Chisnall at cl.cam.ac.uk> writes: > Perhaps I am missing something, but isn't a predicated instruction > effectively an single-instruction version of an arithmetic operation > followed by a select? No, it is not. Among other things, predication is used to avoid traps. A vector select is an entirely different operation. > As we can already represent this in the IR, and alre...

Hi Marcello, I am sure I've seen some postings on the list concerning architectures that support predicated execution and how to map that to LLVM IR, I'm just not sure anymore when and who was involved :). I have implemented your first suggestion for targets that do not have predicated instructions (where control flow to data flow conversion with explicit maintaining of masks and blend operation...

Assume an architecture that has multiple condition code registers, e.g., powerpc. Now assume that there are predicate instructions like thumb2, but can specify which condition code register they refer to. Now also assume that these predicate instructions themselves are predicatible, if executed they change the current predication state. Can LLVM handle multiple levels of predication? When is IfConversion used an...

On Oct 7, 2007, at 12:51 AM, Nikhil A. Patil wrote: > Hi, > > I am planning to generate code for a peculiar architecture with > _no_ branch instructions (!), but with predicated loads and stores > to memory. This means the architecture is not Turing complete, is > going to waste a lot of computation, and any input program that can > hope to get compiled for this architecture must have loops that can > be fully unrolled, and all its functions must get f...

On May 24, 2011, at 12:02 AM, roy rosen wrote: > Hi, > > I was wondering if LLVM supports predicates and conditional execution. > Something like we have in IA64. > There is a register class of predicates and then every instruction may > be predicated by a register from this class. > For example: > > cmp_less p, x, y // p is a predicate which gets the result of x < y > p a...