search for: ppcgendisassemblert

...tures_str” variables used at DisassemblerLLVMC.cpp:1163 > > (“newLLVMCDisassembler(triple_str, cpu, features_str.c_str(), flavor, > *this)”)? > > > > Another question that I have is, how can I compare the data it gets with > the real instructions? > > I found the file “PPCGenDisassemblerTables.inc”, where the table is > declared, and where the it > > is decoded, so the current instruction bne cr7,0x2000092c (0x409e000c) is > being processed by > > the case 30 in the PPCGenDisassemblerTables.inc file: > > case 30: > > tmp = fieldFromInstruc...

...t looks to me right now is that you only get the 64bit registers if the opcode is available exclusively in 64bit mode. I have seen that many instructions have been duplicated to support 32 bit registers and 64 bit register, e.g. oris vs. oris8, but the disassembler does not pick the 64 bit variant. PPCGenDisassemblerTables.inc does not have anything about oris8, only oris. As a user of the Disassembler I would expect it to return me the 64bit instruction referencing the 64bit registers if I ask it to disassemble a ppc64 target. Is this intended behavior or am I just missing some bit somewhere? Thank you very m...

The `isBranch` flag is already set on the branch instructions. Furthermore, we do use the `isBranch()` query in a few places in the PPC back end, so this does work. Perhaps there's something specific about the lldb usage? Is it somehow possible that the `isBranch()` query is called on the wrong instruction? Would you be able to provide a test case that reproduces the issue? On Thu, Nov 30,

I've been working on adding support for a (semi-proprietary) extension for PowerPC called "Paired-Singles". It's a SIMD instruction set supporting various operations on a vector of 2 32-bit floating point numbers. The Extension is found in the PowerPC 750CL, modified variants of it are used in the Nintendo GameCube (Gekko), the Nintendo Wii (Broadway) and the Nintendo Wii U