search for: ppccodeemitter

>> 2) Same error but some diff. problem with AlphaCodeEmitter.cpp and >> PPCCodeEmitter.cpp: >> >> GCC don't like definition member-functions in global namespace with >> declaration in llvm::<unnamed> : Sorry for wrong comment. Must be: GCC 4.1.0 don't like definition member-functions in llvm namespace with declaration in <global>::<unname...

...in including SparcV8GenCodeEmitter.inc: namespace llvm { ... #include "SparcV8GenCodeEmitter.inc" } // end llvm namespace But SparcV8GenCodeEmitter.inc generated with namespace llvm { ... } // end llvm namespace 2) Same error but some diff. problem with AlphaCodeEmitter.cpp and PPCCodeEmitter.cpp: GCC don't like definition member-functions in global namespace with declaration in llvm::<unnamed> : 3) Patch suggested in http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20051017/028898.html move END_WITH_NULL to before function name. Vladimir === Patches =======...

...e/wanderer/pkg/build/llvm/obj/lib/Target/SparcV8/SparcV8GenCodeEmitter.inc:11: > error: definition of 'unsigned int Patch applied: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20051017/028993.html > 2) Same error but some diff. problem with AlphaCodeEmitter.cpp and > PPCCodeEmitter.cpp: > > GCC don't like definition member-functions in global namespace with > declaration in llvm::<unnamed> : Can you try this patch and see if it works? I'd rather not put the entire file in namespace scope like V8: Index: AlphaCodeEmitter.cpp =======================...

Hi all, I'm compiling current SVN HEAD on Linux/x86. The tests are failing on PowerPC due to the following assertion failure : JITTests: PPCCodeEmitter.cpp:152: unsigned int<unnamed>::PPCCodeEmitter:: getMachineOpValue(const llvm::MachineInstr&, const llvm::MachineOperand&) const: Assertion `MovePCtoLROffset && "MovePCtoLR not seen yet?"' failed. Is anyone working on the PowerPC backend? Erik -- -----...

On Mon, 24 Oct 2005, Vladimir A. Merzliakov wrote: >>> 2) Same error but some diff. problem with AlphaCodeEmitter.cpp and >>> PPCCodeEmitter.cpp: >>> >>> GCC don't like definition member-functions in global namespace with >>> declaration in llvm::<unnamed> : > > Sorry for wrong comment. > Must be: > GCC 4.1.0 don't like definition member-functions in llvm namespace with > decla...

Erik de Castro Lopo <mle+cl <at> mega-nerd.com> writes: > > Hi all, > > I'm compiling current SVN HEAD on Linux/x86. The tests are failing > on PowerPC due to the following assertion failure : > > JITTests: PPCCodeEmitter.cpp:152: unsigned int<unnamed>::PPCCodeEmitter:: > getMachineOpValue(const llvm::MachineInstr&, const llvm::MachineOperand&) > const: Assertion `MovePCtoLROffset && "MovePCtoLR not seen yet?"' failed. > > Is anyone working on the PowerPC back...

...o track down where the problem is. Here is the backtrace, (gdb) bt #0 0x00000fffb7b84090 in .raise () from /lib/libc.so.6 #1 0x00000fffb7b85ca4 in .abort () from /lib/libc.so.6 #2 0x0000000010517b9c in ._ZN4llvm25llvm_unreachable_internalEPKcS1_j () #3 0x0000000010047aa0 in ._ZN12_GLOBAL__N_114PPCCodeEmitter17getMachineOpValueERKN4llvm12MachineInstrERKNS1_14MachineOperandE () #4 0x0000000010048ff4 in ._ZN12_GLOBAL__N_114PPCCodeEmitter14emitBasicBlockERN4llvm17MachineBasicBlockE () #5 0x000000001004940c in ._ZN12_GLOBAL__N_114PPCCodeEmitter20runOnMachineFunctionERN4llvm15MachineFunctionE () #6 0x0000...

On Mon, 16 Jun 2008, Gary Benson wrote: > When you genetate code on PowerPC you need to explicitly invalidate > the instruction cache to force the processor to reread it. In LLVM > there is code to do this for function stubs on Macintosh, but not > for other platforms and not for JITted code generally. Applied, thanks!

...uction cache on some + // platforms. + virtual void InvalidateInstructionCache(const void *Addr, unsigned len) {} + /// needsGOT - Allows a target to specify that it would like the // JIT to manage a GOT for it. bool needsGOT() const { return useGOT; } Index: lib/Target/PowerPC/PPCCodeEmitter.cpp =================================================================== --- lib/Target/PowerPC/PPCCodeEmitter.cpp (revision 52391) +++ lib/Target/PowerPC/PPCCodeEmitter.cpp (working copy) @@ -80,10 +80,6 @@ return new PPCCodeEmitter(TM, MCE); } -#ifdef __APPLE__ -extern "C" void sy...

Hi, all I have a trouble with calling external functions on PowerPC. What I am doing is generating a LLVM IR first like this, - x86 call void @helper_shack_flush(%struct.CPUX86State* %62) noinline, !flags !12 - ppc call void @helper_shack_flush(%struct.CPUX86State* %62) noinline, !flags !10 After lowering above LLVM IR for x86 and ppc, it becomes: - x86 %RAX<def> = MOV64ri

Hi all, When you genetate code on PowerPC you need to explicitly invalidate the instruction cache to force the processor to reread it. In LLVM there is code to do this for function stubs on Macintosh, but not for other platforms and not for JITted code generally. The attached patch adds support for GNU platforms, but I can't figure out a nice way to call it for all generated code. Can

Erik de Castro Lopo <mle+cl <at> mega-nerd.com> writes: > > Hi all, > > I'm compiling current SVN HEAD on Linux/x86. The tests are failing > on PowerPC due to the following assertion failure : > > JITTests: PPCCodeEmitter.cpp:152: unsigned int<unnamed>::PPCCodeEmitter:: > getMachineOpValue(const llvm::MachineInstr&, const llvm::MachineOperand&) > const: Assertion `MovePCtoLROffset && "MovePCtoLR not seen yet?"' failed. > > Is anyone working on the PowerPC back...

...B\n\tbne- La${label}_exit", > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > $label)]>; > } > > ...and I can't figure out the syntax for that. Any suggestions? Hi Gary, You have to write custom encoding logic in C++ for this. This should go in PPCCodeEmitter::emitBasicBlock. I admit this isn't very elegant. A better solution would be to fix the lowering to produce two instructions instead of this pseudo instruction. -Chris

Hi all, I'm trying to figure out how to add the instructions required for llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch attached) but the other two (CMP_UNRESw and STWCX) require multiple instructions: let Defs = [CR0] in { def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), "stwcx. $rS, $dst\n\tbne-

...on wrote: > Erik de Castro Lopo <mle+cl <at> mega-nerd.com> writes: > >> >> Hi all, >> >> I'm compiling current SVN HEAD on Linux/x86. The tests are failing >> on PowerPC due to the following assertion failure : >> >> JITTests: PPCCodeEmitter.cpp:152: unsigned int<unnamed>::PPCCodeEmitter:: >> getMachineOpValue(const llvm::MachineInstr&, const llvm::MachineOperand&) >> const: Assertion `MovePCtoLROffset && "MovePCtoLR not seen yet?"' failed. >> >> Is anyone working on th...

...lvm-1.8/debugBuild/../llvm/lib/Target/PowerPC/PPCJITInfo.cpp:205 #4 0x00017c00 in (anonymous namespace)::JITEmitter::finishFunction (this=0x6602f80, F=@0x6604db0) at /Users/andreas/build/llvm-1.8/debugBuild/../llvm/lib/ExecutionEngine/JIT/JITEmitter.cpp:824 #5 0x0005a984 in (anonymous namespace)::PPCCodeEmitter::runOnMachineFunction (this=0x6603f70, MF=@0x6604db0) at /Users/andreas/build/llvm-1.8/debugBuild/../llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp:88 #6 0x003ebfcc in llvm::MachineFunctionPass::runOnFunction (this=0x6603f70, F=@0x6601ff0) at /Users/andreas/build/llvm-1.8/debugBuild/../llvm/include/ll...

I see that JIT isn't supported for the Sparc targets for example. What is the scope of the change to add JIT support. I see, for example, that for X86 target class X86JITInfo is defined with 10 methods. It's only used in one place: setPICBase. Also createX86JITCodeEmitterPass creates JIT pass -- very simple. So is implementing these steps enough to add JIT, or there are some hidden

...hineModuleInfo* MMI) { } > + > /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE! > virtual void startFunctionStub(unsigned StubSize, unsigned > Alignment = 1) { > assert(0 && "JIT specific function called!"); > Index: lib/Target/PowerPC/PPCCodeEmitter.cpp > =================================================================== > --- lib/Target/PowerPC/PPCCodeEmitter.cpp (revision 44794) > +++ lib/Target/PowerPC/PPCCodeEmitter.cpp (working copy) > @@ -38,6 +38,11 @@ > /// getMachineOpValue - evaluates the MachineOperand of a &g...

...ture ObjectCodeEmitter lib/Target/X86/X86JITInfo.h lib/Target/X86/X86JITInfo.cpp * Replaced references to MachineCodeEmitter with JITCodeEmitter. lib/Target/PowerPC/PPC.h lib/Target/PowerPC/PPCTargetMachine.h lib/Target/PowerPC/PPCTargetMachine.cpp lib/Target/PowerPC/PPCCodeEmitter.cpp * Parameterized to support JITCodeEmitter and in future ObjectCodeEmitter lib/Target/PowerPC/PPCJITInfo.h lib/Target/PowerPC/PPCJITInfo.cpp * Replaced references to MachineCodeEmitter with JITCodeEmitter. lib/Target/ARM/ARM.h lib/Target/ARM/ARMTargetMachine.h l...

...>> + >> /// JIT SPECIFIC FUNCTIONS - DO NOT IMPLEMENT THESE HERE! >> virtual void startFunctionStub(unsigned StubSize, unsigned >> Alignment = 1) { >> assert(0 && "JIT specific function called!"); >> Index: lib/Target/PowerPC/PPCCodeEmitter.cpp >> =================================================================== >> --- lib/Target/PowerPC/PPCCodeEmitter.cpp (revision 44794) >> +++ lib/Target/PowerPC/PPCCodeEmitter.cpp (working copy) >> @@ -38,6 +38,11 @@ >> /// getMachineOpValue - evaluates the Mach...