search for: postincr

...the vienna university of technology in the recent past. our approach considers ssa graphs and is based on a problem transformation to a specialized quadratic assignment problem (pbqp). in contrast to previous work [1], the technique is flexible enough to cope with general DAG patterns such as pre/postincrement or divmod patterns. the instruction selector is a drop-in replacement for the original implementation (llvm 2.1). we've used the ARM backend for evaluation and obtained quite encouraging results: speedups are up to 10% for SPEC/Mibench and up to 57% for simple loop kernels. the compile...

...t; > Cc: "<llvmdev at cs.uiuc.edu>" <llvmdev at cs.uiuc.edu> > Sent: Thursday, October 23, 2014 8:31:35 AM > Subject: Re: [LLVMdev] Question regarding getElementPtr/Addressing modes in backend > > Many CPU instruction sets have "autoincrement" / "postincrement" > (pop) / "predecrement" (push) instructions that dereference a > pointer register and also alter it by the size of the load or store. > > > The PowerPC has "load byte/short/word with update" instructions that > add an arbitrary positive or negativ...

Hi Steve, Thanks for the tip regarding MIOperandInfo, I didn't think of that part of the tablegen description. Sadly, I did actually mean: r1 = *(i0 += m0). So increment i0 by m0. Read memory the memory location "pointed" to by i0. Store in r1. Sadly I am not too familiar with compiler terminology, so I don't know if there is a proper term for such a load. On Thu, Oct 23,

...tructions. The binary encoding is not particularly consistent -- take a look at this table of variants of LD, along with their machine code representation: # load 8 bits from pointer register X into general purpose Rd ld Rd, X `1001 000d dddd 1100` ld Rd, X+ `1001 000d dddd 1101` (load with postincrement) ld Rd, -X `1001 000d dddd 1110` (load with predecrement) ld Rd, Y `1000 000d dddd 1000` ld Rd, Y+ `1001 000d dddd 1001` ld Rd, -Y `1001 000d dddd 1010` ld Rd, Z `1000 000d dddd 0000` ld Rd, Z+ `1001 000d dddd 0001` ld Rd, -Z `1001 000d dddd 0010` ^...

...technology in the recent past. our approach > considers ssa graphs and is based on a problem transformation to a > specialized quadratic assignment problem (pbqp). in contrast to > previous > work [1], the technique is flexible enough to cope with general DAG > patterns such as pre/postincrement or divmod patterns. > > the instruction selector is a drop-in replacement for the original > implementation (llvm 2.1). we've used the ARM backend for evaluation > and > obtained quite encouraging results: speedups are up to 10% for > SPEC/Mibench and up to 57% for simp...

...gjmp for the m68k architecture +# + +# +# The jmp_buf is assumed to contain the following, in order: +# %d2..%d7 +# %a2..%a7 +# return address +# + + .text + .align 2 + .globl setjmp + .type setjmp, @function +setjmp: + move.l (%sp)+, %d0 | Return address + movea.l (%sp), %a0 | Buffer address + | Postincrement mode is not permitted here... + movem.l %d2-%d7/%a2-%a7, (%a0) + move.l %d0, 48(%a0) | Return address + move.l %d0, -(%sp) | Restore return address + clr.l %d0 | Return value + movea.l %d0, %a0 | Redundant return... + rts + + .size setjmp,.-setjmp + + .text + .align 2 + .globl longjmp + ....

On Mar 24, 2008, at 10:47 PM, Christopher Lamb wrote: > I know that this has been discussed (at least in passing) a few > times on the list, but I couldn't locate a bug for it. Have any > architectural plans been made for it? Funny you bring this up. Evan and I were tossing around crazy ideas about this just today. If you're interested, maybe we should get together for

I know that this has been discussed (at least in passing) a few times on the list, but I couldn't locate a bug for it. Have any architectural plans been made for it? Are there architectural roadblocks with the current LLVM infrastructure that will complicate the process? What has demotivated the implementation of this so far (is it not that big a benefit on important targets, too

Thanks. I saw the header comments but it wasn’t clear to me what the difference between those concepts is? My slightly vague understanding is IsDef means that the register specified by this operand is set by the machine instruction. So I understand that to mean the MO will override that register? Also things like early clobber, perhaps there is another document that clarifies some of these

...nitialized anchor (Coverity). propsys: PropVariantClear does not clear on uninitialized values (Coverity). dinput: Added a missing close(fd) in disabled case (Coverity). shlwapi: Fixed incorrect buffer size. Matteo Bruni (27): d3dcompiler: Parse swizzles. d3dcompiler: Postincrement/decrement expressions are const. d3dcompiler: Stub D3DDisassemble. d3dcompiler: Declare predefined data types. d3dcompiler: Don't write the shader version tag from the header backend function. d3dcompiler: Only a few modifiers are relevant in type comparison....

I have updated the klibc patchset based on feedback received. In particular, the patchset has been reorganized so as not to break git-bisect. Additionally, this updates the patch base to 2.6.17-git12 (d38b69689c349f35502b92e20dafb30c62d49d63) and klibc 1.4.8; the main difference on the klibc side is removal of obsolete code. This is also available as a git tree at: