search for: postinc

I'm happy to announce that Apple is contributing some major extensions to the LLVM ARM backend. The improvements include support for ARM v4/v6, vfp support, soft float, pre/postinc support, load/ store multiple generation, constant pool entry motion (to support large functions), and support for the darwin/arm ABI. In addition to ARM support, the backend now includes code generation support for the Thumb instruction set, which is effectively a completely new and diff...

...y no way for loop strength reduction to target pre- and post-increment addressing modes. This is because the target hook `isLegalAddressingMode` in TargetTransformInfo.h doesn’t allow for pre- and post-increment. There is in fact a comment to that effect on the function prototype: “TODO: handle pre/postinc as well” (see http://llvm.org/docs/doxygen/html/TargetTransformInfo_8h_source.html line 310). So I was wondering: is there a way to work around this limitation? And are there any plans to add support for pre- and post-increment addressing modes? Thanks in advance for any help on this. Jamie Hanl...

...he icmp from being transformed to post-inc form in OptimizeLoopTermCond() before the initial formulae are determined. Luckily, I was able to remove the redundant add instruction with this hack, but I really doubt if it make sense to prevent a loop terminating condition from being changed to postinc form when it's already a post-inc user. # Input IR : define void @foo(i32 %n, i32* %P) { entry: %cmp7 = icmp sgt i32 %n, 1 br i1 %cmp7, label %for.body.preheader, label %for.end for.body.preheader: ; preds = %entry %n_sext = sext i32 %n to i64 br lab...

...tructions. The binary encoding is not particularly consistent -- take a look at this table of variants of LD, along with their machine code representation: # load 8 bits from pointer register X into general purpose Rd ld Rd, X `1001 000d dddd 1100` ld Rd, X+ `1001 000d dddd 1101` (load with postincrement) ld Rd, -X `1001 000d dddd 1110` (load with predecrement) ld Rd, Y `1000 000d dddd 1000` ld Rd, Y+ `1001 000d dddd 1001` ld Rd, -Y `1001 000d dddd 1010` ld Rd, Z `1000 000d dddd 0000` ld Rd, Z+ `1001 000d dddd 0001` ld Rd, -Z `1001 000d dddd 0010` ^...

...post inc, not the load, but since the DAG combiner simply scans top-down, the opposite happens. So here is the question - do you recognize this as a deficiency, and can you see the same in PPC? The fix is code trivial, but it would introduce a general concept of a primitive cost function to the PostInc candidacy selection in DAG combine. If you recognize the issue, I will post a patch with more details, but if I am missing the big picture here, please advise. Sergei --- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

...ent the icmp from being transformed to post-inc form in OptimizeLoopTermCond() before the initial formulae are determined. Luckily, I was able to remove the redundant add instruction with this hack, but I really doubt if it make sense to prevent a loop terminating condition from being changed to postinc form when it's already a post-inc user. I agree, but don’t have a better suggestion. You could file a bug. Anyone have time to try out some fixes? Andy > # Input IR : > > define void @foo(i32 %n, i32* %P) { > entry: > %cmp7 = icmp sgt i32 %n, 1 > br i1 %cmp7, label %for....

...e DAG combiner simply scans > top-down, the opposite happens. > > So here is the question - do you recognize this as a deficiency, > and can > you see the same in PPC? The fix is code trivial, but it would > introduce a > general concept of a primitive cost function to the PostInc candidacy > selection in DAG combine. If you recognize the issue, I will post a > patch > with more details, but if I am missing the big picture here, please > advise. > > Sergei > > > --- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > hos...

...ans top-down, the opposite happens. > > > > So here is the question - do you recognize this as a deficiency, > > and can > > you see the same in PPC? The fix is code trivial, but it would > > introduce a general concept of a primitive cost function to the > > PostInc candidacy selection in DAG combine. If you recognize the > > issue, I will post a patch with more details, but if I am missing the > > big picture here, please advise. > > > > Sergei > > > > > > --- > > Qualcomm Innovation Center, Inc. is a member of...

...hat is the theory, any failures should get fixed. The only missing C language feature/extension I know of now is inline asm, which is currently being worked on. It has support for varargs and variable sized allocas. The backend has support for 95% of the ISA, including all adressing modes (predec, postinc and indexed) for both data and program address spaces. Currently, the only code emission mode supported is text, in the future object file emission should be implemented, for now we require an external assembler and linker. No support now for subtargets. Regarding optimizations, it has very few im...

...be used in the Apple iPhone? >>> Eric On Jan 17, 2007, at 2:11 AM, Chris Lattner wrote: > > I'm happy to announce that Apple is contributing some major > extensions to the LLVM ARM backend. The improvements include support > for ARM v4/v6, vfp support, soft float, pre/postinc support, load/ > store multiple generation, constant pool entry motion (to support > large functions), and support for the darwin/arm ABI. In addition to > ARM support, the backend now includes code generation support for the > Thumb instruction set, which is effectively a completely n...

----- Original Message ----- > From: "Paul Redmond" <paul.redmond at intel.com> > To: "llvmdev at cs.uiuc.edu Dev" <llvmdev at cs.uiuc.edu> > Sent: Thursday, February 28, 2013 1:30:57 PM > Subject: [LLVMdev] parallel loop metadata simplification > > Hi, > > I've been working on clang codegen for #pragma ivdep and creating the >

...afael contributed several improvements to the ARM backend, including basic inline asm support, weak linkage support, static ctor/dtor support and many bug fixes. 29. Evan contributed major enhancements to the ARM backend, including support for ARM v4-v6, vfp support, soft float, pre/postinc support, load/store multiple generation, and constant pool entry motion (to support large functions). 30. Evan contributed support for Thumb code generation (an ARM subtarget). 31. The PowerPC 64 JIT now supports addressing code loaded above the 2G boundary. 32. Nick Lewycky...

Hi, I've been working on clang codegen for #pragma ivdep and creating the llvm.mem.parallel_loop_access metadata seems quite difficult. The main problem is that there are so many places where loads and stores are created and all of them need to be changed when emitting a parallel loop. Note that creating llvm.loop.parallel is not a problem. One option is to modify IRBuilder to enable

...LLVM : : CodeGen/PowerPC/div-2.ll LLVM : : CodeGen/PowerPC/fp-branch.ll LLVM : : CodeGen/PowerPC/iabs.ll LLVM : : CodeGen/PowerPC/indirectbr.ll LLVM : : CodeGen/PowerPC/int-fp-conv-0.ll LLVM : : CodeGen/PowerPC/int-fp-conv-1.ll LLVM : : CodeGen/PowerPC/lsr-postinc-pos.ll LLVM : : CodeGen/PowerPC/ppc32-vaarg.ll LLVM : : CodeGen/PowerPC/ppcf128-4.ll LLVM : : CodeGen/PowerPC/rlwimi-keep-rsh.ll LLVM : : CodeGen/PowerPC/rlwimi3.ll LLVM : : CodeGen/PowerPC/select-cc.ll LLVM : : CodeGen/PowerPC/shift128.ll LLVM : : CodeGen/...

Hello, the following patches should get multidisk access working. The syntax accepted is the following: (hdx,y)/path/to/file where x is the disk number and start at 0 and the y is the partition number starting at 1. So (hd0,1) is the first partition of the first disk. the other accepted syntax is using MBR's 32 bits disk signature so for example: (mbr:0x12345678,2)/foo/bar would address