Displaying 5 results from an estimated 5 matches for "portidx".
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portid
2012 Jun 19
1
help with xy.coords(x,y)
...nds in my portfolio with 7 different strategies.
"FundName"(fundNames), "fundStrats", "Return"(fundrets)
Here is my code:
for(i in 1:T){
# T equals to the amount of strategies in my portfolio
strat = portStrats[i];
#get strategy
portidx = fundStrats == strat;
# identify portfolio funds of the same strategy
frets = fundrets[portidx];
fnames = fundNames[portidx];
#get returns and names,? frets?: fund return, ?fnames?:fund name
N = length(frets);
s = 1 / N; #now figure out where to put the labels
for (j in 1...
2012 Jun 14
1
Help for boxplot
...its name.
#label portfolio funds
for(i in 1:T){
#loop through all strategies
#get strategy
strat = portStrats[i];
#identify all funds of that strategy
idx = allFundStrats == strat;
#get returns of the all funds
rets = allFundRets[idx];
#identify portfolio funds of the same strategy
portidx = fundStrats == strat;
#get returns and names
frets = fundrets[portidx];
fnames = fundNames[portidx];
N = length(frets);
#now figure out where to put the labels
s = 1 / N;
for (j in 1:N){
yy = j * s + i*2;
points(x=frets[j],y=yy,col="red");
textxy(X=frets[j]*-1,Y=yy,la...
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
...Y_WITH_P2], [II_MUL]>;
>
> where n_LATENCY_WITH_p is defined roughly as:
>
> class n_LATENCY_WITH_p<int latency, ProcResourceKind port> : SchedWriteRes<[PR_Pp]> {
> let Latency = latency;
> let ResourceDelays = [latency];
> }
>
> class PR_Pp<int portIdx> : ProcResource<1>;
>
> The latency for register write-back/port access is static and without interlock, which I think means the port resources should have 'Buffered = 0' in the definition. Is that correct?
Yes, but it isn’t sufficient. The scheduler makes no attempt to ins...
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
...H_p is defined roughly as:
>>>
>>> class n_LATENCY_WITH_p<int latency, ProcResourceKind port> : SchedWriteRes<[PR_Pp]> {
>>> let Latency = latency;
>>> let ResourceDelays = [latency];
>>> }
>>>
>>> class PR_Pp<int portIdx> : ProcResource<1>;
>>>
>>> The latency for register write-back/port access is static and without interlock, which I think means the port resources should have 'Buffered = 0' in the definition. Is that correct?
>>
>> Yes, but it isn’t sufficient. The...
2014 Feb 28
2
[LLVMdev] Question about per-operand machine model
On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote:
> Hi Andy,
>
> I am trying to schedule and packetize instructions for VLIW at post-RA
> stage or final codegen stage, where code transformations are not allowed
> any more, because hardware can not resolve resource conflict. There is a
> simple example as following:
>
> ADD dest_reg1, src_reg1,