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2005 Nov 04
0
TSC and Power Management Events on AMD Processors
...fication is given to the OS when STPCLK-throttling occurs and only chipset-specific methods exist to detect whether a platform is planning on using it.) The BIOS enables the STPCLK-throttling mechanism in the southbridge and programs the processor''s response to it in the PMM5 registers of the integrated northbridge. (Many BIOSes by default program PMM5 for this even if the chipset is not able or configured to generate the STPCLK-throttling message.) STPCLK-throttling ramps up and down the clock grid of all cores on a processor equally, therefore it can not...