search for: mm5

...error_2 - ; dword [esp + 12] == last_error_3 - ; eax == error ; ebx == &data[i] ; ecx == loop counter (i) - ; edx == temp - ; edi == save ; ebp == order ; mm0 == total_error_1:total_error_0 - ; mm1 == total_error_3:total_error_2 - ; mm2 == 0:total_error_4 - ; mm3/4 == 0:unpackarea - ; mm5 == abs(error_1):abs(error_0) - ; mm5 == abs(error_3):abs(error_2) + ; mm1 == total_error_2:total_error_3 + ; mm2 == :total_error_4 + ; mm3 == last_error_1:last_error_0 + ; mm4 == last_error_2:last_error_3 - pxor mm0, mm0 ; total_error_1 = total_error_0 = 0 - pxor mm1, mm1 ; total_error_3 = to...

quite some speed improvement indeed. attached the updated patch to apply to svn/trunk. j -------------- next part -------------- A non-text attachment was scrubbed... Name: theora-mmx.patch.gz Type: application/x-gzip Size: 8648 bytes Desc: not available Url : http://lists.xiph.org/pipermail/theora-dev/attachments/20040824/5a5f2731/theora-mmx.patch-0001.bin

..._pix[0..8] */ +"lea (%1,%1,2),%%esi\n" /* esi = _ystride*3 */ +"movq (%0,%%esi),%%mm4\n" /* mm4 = _pix[0..8]+_ystride*3] */ +"movq %%mm7,%%mm6\n" /* mm6 = _pix[0..8] */ +"punpcklbw %%mm0,%%mm6\n" /* expand unsigned _pix[0..3] to 16 bits */ +"movq %%mm4,%%mm5\n" +"punpckhbw %%mm0,%%mm7\n" /* expand unsigned _pix[4..8] to 16 bits */ +"punpcklbw %%mm0,%%mm4\n" /* expand other arrays too */ +"punpckhbw %%mm0,%%mm5\n" +"psubw %%mm4,%%mm6\n" /* mm6 = mm6 - mm4 */ +"psubw %%mm5,%%mm7\n" /* mm7 = mm7 - mm5...

Dear all, I wrote the following batch script on a iMac, and ran it on a linux mosix cluster. tu <- read.table("cage.mm5.tags.rna_lib.CAA-CAJ.tu-reshape.table") tu_reshaped <- t(reshape(tu[1:50,], direction="wide", timevar="tu", idvar=c("rna","lib"))) write.table(tu_reshaped, "cage.mm5.tags.rna_lib.CAA-CAJ.tu-reshaped.table") q(sav="no") (I will rem...

#I am trying to understand how R fits models for contrasts in a #simple one-way anova. This is an example, I am not stupid enough to want #to simultaneously apply all of these contrasts to real data. With a few #exceptions, the tests that I would compute by hand (or by other software) #will give the same t or F statistics. It is the contrast estimates that R produces #that I can't seem to

Hi Urban smbfs modifies some memory after free... smb_get_length: Invalid NBT packet, code=4a smb_add_request: request [d828617c, mid=1802201963] timed out! Slab corruption: start=d828617c, expend=d8286287, problemat=d8286184 Last user: [<ec992e35>](smb_free_request+0x45/0x4c [smbfs]) Data: ********6A

...t; pxor %%mm0, %%mm0 \n\t" /* zero mm0 */ +" movq (%4), %%mm2 \n\t" /* load mm2 with _src1 */ +" .balign 16 \n\t" +"1: movq (%6), %%mm4 \n\t" /* packed SRC2 */ +" movq %%mm2, %%mm3 \n\t" /* copy to mm3 */ +" movq %%mm4, %%mm5 \n\t" /* copy packed src2 to mm5 */ +" mov %3, %%eax \n\t" +" punpcklbw %%mm0, %%mm2 \n\t" /* expand low part of src1 to mm2 */ +" punpcklbw %%mm0, %%mm4 \n\t" /* low part expand of src2 to mm4 */ +" lea (%4,%%eax), %4 \n\t" /* _src1+_src1_ys...

Fellow users, I'm running into some rather odd behavior trying to compile some software, and would like to know if there is maybe a fix or if I should revert back to a 32-bit version of Centos. I'm trying to compile NCAR Graphics, as well as some other weather related software on this machine which is running the Centos 4.1 x86-64 version. It's a dual Xeon processor.

...proposal is to replace all functions in assembly with compiler intrinsic which compiles into 1-2 assembly instructions and are much easier to maintain. For example: _mm_sad_epu8(__m128, __m128) will be compiled in PSADBW instruction with compiler-allocated registers. And code like: psadbw mm4,mm5 paddw mm0,mm4 Can be re-written into _m64 mm0, mm4, mm5, mm6, mm7; //of course using meaningful names mm0= _mm_add_epi16(mm0, _mm_sad_pu8(mm4, mm5)); Compiler will replace variables with actual registers, ensuring better allocation and scheduling of them. So, benefits are: 1) Easier to read...

Hi, First ,please excuse my poor English. Can someone help me on reading fortran binary object under R? I was trying to read mm5 data under R. However, I seem to stuck at reading fortran binary file storing met. data array. At the beginning, I used readBin() to read mm5 output directly with the following command. #mmout is a mmout file generated with mm5 >mm5file<-file("mmout","rb") >readBin(mm5f...

...t; pxor %%mm0, %%mm0 \n\t" /* zero mm0 */ +" movq (%4), %%mm2 \n\t" /* load mm2 with _src1 */ +" .balign 16 \n\t" +"1: movq (%6), %%mm4 \n\t" /* packed SRC2 */ +" movq %%mm2, %%mm3 \n\t" /* copy to mm3 */ +" movq %%mm4, %%mm5 \n\t" /* copy packed src2 to mm5 */ +" mov %3, %%eax \n\t" +" punpcklbw %%mm0, %%mm2 \n\t" /* expand low part of src1 to mm2 */ +" punpcklbw %%mm0, %%mm4 \n\t" /* low part expand of src2 to mm4 */ +" lea (%4,%%eax), %4 \n\t" /* _src1+_src1_ys...

...gs I >> added, however the calling code did not change at all... > > Look in X86InstrControl.td. The call instructions are all prefixed > by: > > let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, FP0, FP1, FP2, > FP3, FP4, FP5, FP6, ST0, ST1, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, > XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, > XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], > > This is the fixed list of call-clobbered registers. It should really > be controlled by the calling convention of the called function > instead. >...

...i want to calculate the monthly mean for the time how can i make that , is there any function doing that Thanks a lot ##load rgl package library(rgl) library(fields) library(ncdf) library(scatterplot3d) ## open binary file to read nc <- open.ncdf("/srv/ccrc/data05/z3236814/mm5/co2/2000/q.200001.mon.nc") v1 <- nc$var [[1]] v2 <- nc$var [[2]] v3 <- nc$var [[3]] data1 <- get.var.ncdf(nc,v1) data2 <- get.var.ncdf(nc,v2) data3 <- get.var.ncdf(nc,v3) coldat = data1[1:111,1:101,23,1:60] ## creat colour hcol = cumsum(coldat) coldat = hcol hcol = hc...

...: > On 20.10.2010 05:00, Jakob Stoklund Olesen wrote: >> Look in X86InstrControl.td. The call instructions are all prefixed >> by: >> >> let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, FP0, FP1, FP2, >> FP3, FP4, FP5, FP6, ST0, ST1, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, >> XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, >> XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], >> >> This is the fixed list of call-clobbered registers. It should really >> be controlled by the calling convention of the called function...

...10 05:00, Jakob Stoklund Olesen wrote: >>> Look in X86InstrControl.td. The call instructions are all prefixed >>> by: >>> >>> let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, FP0, FP1, FP2, >>> FP3, FP4, FP5, FP6, ST0, ST1, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, >>> XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, >>> XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], >>> >>> This is the fixed list of call-clobbered registers. It should really >>> be controlled by the calling convention of...

...m regs I > added, however the calling code did not change at all... Look in X86InstrControl.td. The call instructions are all prefixed by: let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], This is the fixed list of call-clobbered registers. It should really be controlled by the calling convention of the called function instead. The WI...

...187, 169, 189, 168, 182, 208, 207, 193, 144, 178, 177, 176, 205, 153, 228, 227, 147, 173, 157, 214, 167, 140, 179, 204, 184, 151, 115, 173, 208, 135, 175, 136, 121, 189, 148, 174), .Names = c("Lead1.mm1", "Lead1.mm2", "Lead1.mm3", "Lead1.mm4", "Lead1.mm5", "Lead1.mm6", "Lead1.mm7", "Lead1.mm8", "Lead1.mm9", "Lead1.mm10", "Lead1.mm11", "Lead1.mm12", "Lead1.mm13", "Lead1.mm14", "Lead1.mm15", "Lead1.mm16", "Lead1.mm17", "...

...the case that it's in multiple classes). Does ValueType have something to do with that? In the same file, the VR64 register class has the following definition: def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32, v1i64], 64, [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>; So there are multiple ValueTypes here (the scalar registers each only have one corresponding to the bit size of the register). But still, if I have physical register MM2, that completely determines its register class. Is there some other architecture where the physical register...

Thanks for giving it a look! On 19.10.2010 23:21, Jakob Stoklund Olesen wrote: > On Oct 19, 2010, at 11:40 AM, Roland Scheidegger wrote: > >> So I saw that the code is doing lots of register >> spilling/reloading. Now I understand that due to calling >> conventions, there's not really a way to avoid this - I tried using >> coldcc but apparently the backend

...ef,dead>, %FP3<imp-def,dead>, %FP4<imp-def,dead>, %FP5<imp-def,dead>, %FP6<imp-def,dead>, %ST0<imp-def,dead>, %ST1<imp-def,dead>, %MM0<imp-def,dead>, %MM1<imp-def,dead>, %MM2<imp-def,dead>, %MM3<imp-def,dead>, %MM4<imp-def,dead>, %MM5<imp-def,dead>, %MM6<imp-def,dead>, %MM7<imp-def,dead>, %XMM0<imp-def,dead>, %XMM1<imp-def,dead>, %XMM2<imp-def,dead>, %XMM3<imp-def,dead>, %XMM4<imp-def,dead>, %XMM5<imp-def,dead>, %XMM6<imp-def,dead>, %XMM7<imp-def,dead>, %XMM8<i...