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...ctivating MIPS Code Emitter. Hi Jafar, That’s not quite what I meant. Why do you need to know the exact encoding at all? The instruction opcode+operands should have all the semantic information you need without ever looking at the actual encoding. -Jim On May 30, 2013, at 11:08 AM, Jafar J <pluck90 at hotmail.com> wrote: Yes your absolutely right, the Opcode and the Operands in each machine instruction are sufficient to generate the final binary representation of the MachineInstruction but not exactly. If you take a look at the format of each MIPS instruction, you’ll see that there are...

On May 30, 2013, at 11:35 AM, Jafar J <pluck90 at hotmail.com> wrote: > Hi Jim, > > The idea of reducing the switching activity between the instructions works by reducing the hamming distance between tow consecutive binary strings across the basic block, or reducing the number of the different bits between two consecutive instruc...

...about solving this problem, though. Are the instruction opcode (MachineInstr::getOpcode()) and the operand values not sufficient? All the information present in the encoding should be inferable from those, as that’s where the encoding comes from. -Jim On May 30, 2013, at 10:12 AM, Jafar J <pluck90 at hotmail.com> wrote: I need to represent each instruction with its (32-bit) binary encoding, and I reached to a conclusion that I could get the encoding through the MipsCodeEmitter. What I’m trying to do exactly is write a scheduler which tries to minimize the switching activity between th...

Hi Jafar, That’s not quite what I meant. Why do you need to know the exact encoding at all? The instruction opcode+operands should have all the semantic information you need without ever looking at the actual encoding. -Jim On May 30, 2013, at 11:08 AM, Jafar J <pluck90 at hotmail.com> wrote: > Yes your absolutely right, the Opcode and the Operands in each machine instruction are sufficient to generate the final binary representation of the MachineInstruction but not exactly. If you take a look at the format of each MIPS instruction, you’ll see that there a...

...h Sent: Thursday, May 30, 2013 7:55 PM To: Jafar J Cc: llvmdev at cs.uiuc.edu ; Mailing List Subject: Re: [LLVMdev] Activating MIPS Code Emitter. What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTarget...

...o about solving this problem, though. Are the instruction opcode (MachineInstr::getOpcode()) and the operand values not sufficient? All the information present in the encoding should be inferable from those, as that’s where the encoding comes from. -Jim On May 30, 2013, at 10:12 AM, Jafar J <pluck90 at hotmail.com> wrote: > I need to represent each instruction with its (32-bit) binary encoding, and I reached to a conclusion that I could get the encoding through the MipsCodeEmitter. What I’m trying to do exactly is write a scheduler which tries to minimize the switching activity between...

What are you actually trying to do? The code emitters have nothing to do with the post-RA scheduler. -Jim On May 30, 2013, at 6:23 AM, Jafar J <pluck90 at hotmail.com> wrote: > Hello, > > Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/...

Hello, Is it possible to activate the MIPS code emitter during Post-RA scheduler. I tried including both MipsCodeEmitter.cpp and JITCodeEmitter.h to PostRASchedulerList.cpp, but when I rebuild the compiler I get an error that says “/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h fatal error: MipsGenRegisterInfo.inc file not found”. I’m assuming that the MipsGenRegisterInfo.inc is not yet

Hello, why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM. Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120818/a8e4f353/attachment.html>

Hello, I have two questions I want to ask. The first one, where is the post register allocation instruction scheduler function is called, and whether it could be called for both x86 and MIPS ? The second question, is it possible to get the complete binary representation of some instruction (<= 32-bit binary encoding) for both x86 and MIPS in post register allocation instruction scheduler, and

Hello, Considering the following MachineInstruction dumped by some SUnit for MIPS target in PostRA-Scheduling “%A1<def> = ADDiu %ZERO, 30”, and the format for the ADDiu instruction is ADDiu rt, rs, immediate. The encoding for the instruction is 001001 rs rt immediate, with lengths of 6, 5, 5, 16 respectively. My question is how to map the operands with their right register? i.e. %A1 = rt,

Hello, Is it possible to pass the two parameters -march=arm and –mcpu=cortex-a5 to llc through DragonEgg’s –fplugin-arg-dragonegg-llvm-option in order to produce an ARM object file? Thanks, Jafar J. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130814/ff5ce014/attachment.html>

Hello, I know that this question is off-topic for the llvm mailing list but I did a lot o search to find an answer, posted questions on other sites and it’s still now working so I decided to post my question here. So, I would really appreciate the help. I’m using llvm-gcc 4.2-2.9 front-end with llvm 2.9 back-end. For about seven months now I’ve been doing the development using text viewers,