search for: plls

...ramgk104.c index 8bcb7e79a0cb..456aed1f2a02 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -1070,7 +1070,7 @@ gk104_ram_calc_xits(struct gk104_ram *ram, struct nvkm_ram_data *next) nvkm_error(subdev, "unable to calc plls\n"); return -EINVAL; } - nvkm_debug(subdev, "sucessfully calced PLLs for clock %i kHz" + nvkm_debug(subdev, "successfully calced PLLs for clock %i kHz" " (refclock: %i kHz)\n", next->freq, ret); } else { /* calculate refpll coefficients */ --...

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

Fixes regression introduced in commit 70790f4f "drm/nouveau/clock: pull in the implementation from all over the place" When code was moved from nv50_crtc_set_clock to nvc0_clock_pll_set, the PLLs it is used for got limited to only the first two VPLLs. nv50_crtc_set_clock was only called to change VPLLs, so it didn't limit what it was used for in any way. Since nvc0_clock_pll_set is used for all PLLs, it has to specify which PLLs the code is used for, and only listed the first two VPLLs...

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but

this is my first patch on the list through git send-mail and I hope everything is set up right, sorry for the noise here, but I don't want to try with an empty mail :) as the subject already says, this patch fixes one of the more serious issues while reclocking gddr5 on kepler cards. It works for me and for a bunch of others I met on IRC. Karol Herbst (1): pll/gk104: fix PLL instability

.... On the last level there is usually a Phase-Lock > Loop (PLL) that can take either the original clock or one of several > divided clocks as an input, and bring this clock up to the desired > level for the associated subcomponent. Control registers alter the > precise input of these PLLs, and can in addition be configured to > bypass the PLLs. > > The video BIOS (VBIOS) provides two services: it takes care of > bringing the GPU in to an initial valid state, and it contains crucial > information regarding reclocking. Most importantly, the VBIOS > describes the...

Resend of patch #7 to fix behaviour when failing to pause parts of the GPU

...5:09 2006 Quartus II Version : 5.1 Build 176 10/26/2005 SJ Revision Name : idctslow Top-level Entity Name : IDctSlow Family : Stratix II Total combinational functions : 13782 Total registers : 3451 Total pins : 54 Total virtual pins : 0 Total memory bits : 2,048 DSP block 9-bit elements : 230 Total PLLs : 0 Total DLLs : 0 ------------------------------------ These numbers are no good. Im using (on this first version) a RAM like an array, acessing every time , without worry. But, It inferrs flipflops for each memory position, and big muxes to control it. So, to solve this problem, I will use a s...

...Name : IDctSlow Family : Stratix II Device : EP2S60F672C5ES Timing Models : Final Total ALUTs : 2,538 / 48,352 ( 5 % ) Total registers : 466 Total pins : 54 / 493 ( 11 % ) Total virtual pins : 0 Total memory bits : 3,072 / 2,544,192 ( < 1 % ) DSP block 9-bit elements : 2 / 288 ( < 1 % ) Total PLLs : 0 / 6 ( 0 % ) Total DLLs : 0 / 2 ( 0 % ) -- ________________________________________ Felipe Portavales <portavales@gmail.com> Undergraduate Student - IC-UNICAMP Computer Systems Laboratory http://www.lsc.ic.unicamp.br

...AGE----- Hash: SHA1 I think we are getting close to a "gold" release here. - - added MacModel support for the mini - - fixed Xv crasher - - lots of LVDS fixes - - external tmds should work again (assuming the external chip is bios inited) Alex Deucher (13): RADEON: round 3 on the PLLs. should fix the LVDS issues RADEON: fix up dvo support (still no external chip init) RADEON: remove more old cruft RADEON: RMX updates RADEON: Fix RMX on LVDS RADEON: preliminary support for mac mini RADEON: Don't make the entity as shareable Revert &q...

We have a local time server and all of our machines are pointed at it for the time. How can the clock drift by a day and a half? [root at devserver21 ~]# date Fri Aug 13 14:43:29 EDT 2010 [root at devserver21 ~]# rdate -s 192.168.1.67 [root at devserver21 ~]# date Thu Aug 12 07:02:39 EDT 2010 [root at devserver21 ~]# cat /etc/ntp.conf | grep -v ^# | grep -v ^$ restrict default nomodify notrap

...in at alum.mit.edu>: > [clipped a bit so that it doesn't get held up by moderator, i've left > the relevant dmesg bits in] > > On Fri, Jun 12, 2015 at 3:47 AM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: > > Hm, well you can see the messages about failure to set plls, which is why > > you don't see anything. The only odd thing I see is that you're using > vesa, > > which can definitely mess things up. Try not using that. Also try booting > > with nouveau.debug=debug drm.debug=0xe which might provide more relevant > > info. &gt...

...clk, 0x4070, priv->spost); + pllmask |= (0x3 << 12); + mast |= 0x00000030; + break; + default: + nv_warn(priv,"Reclocking failed: unknown sclk clock\n"); + goto resume; + } + + if (!nv_wait(clk, 0x004080, pllmask, pllmask)) { + nv_warn(priv,"Reclocking failed: unstable PLLs\n"); + goto resume; + } + + switch (priv->vsrc) { + case nv_clk_src_cclk: + mast |= 0x00400000; + default: + nv_wr32(clk, 0x4600, priv->vdiv); + } + + nv_wr32(clk, 0xc054, mast); + ret = 0; + +resume: + if (pfifo) + pfifo->start(pfifo, &flags); + + nv_mask(clk, 0x002504, 0x000...

...clk, 0x4070, priv->spost); + pllmask |= (0x3 << 12); + mast |= 0x00000030; + break; + default: + nv_warn(priv,"Reclocking failed: unknown sclk clock\n"); + goto resume; + } + + if (!nv_wait(clk, 0x004080, pllmask, pllmask)) { + nv_warn(priv,"Reclocking failed: unstable PLLs\n"); + goto resume; + } + + switch (priv->vsrc) { + case nv_clk_src_cclk: + mast |= 0x00400000; + default: + nv_wr32(clk, 0x4600, priv->vdiv); + } + + nv_wr32(clk, 0xc054, mast); + ret = 0; + +resume: + if (pfifo) + pfifo->start(pfifo, &flags); + + nv_mask(clk, 0x002504, 0x000...

...st = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640); @@ -378,12 +366,6 @@ nvaa_clock_prog(struct nouveau_clock *clk) ret = 0; resume: - if (pfifo) - pfifo->start(pfifo, &flags); - - nv_mask(clk, 0x002504, 0x00000001, 0x00000000); - nv_wr32(clk, 0x020060, ptherm_gate); - /* Disable some PLLs and dividers when unused */ if (priv->csrc != nv_clk_src_core) { nv_wr32(clk, 0x4040, 0x00000000); @@ -395,6 +377,8 @@ resume: nv_mask(clk, 0x4020, 0x80000000, 0x00000000); } + nva3_clock_post(clk, &flags); + return ret; } -- 1.9.3

Re-resend of patch #7 to move the _post and _pre function prototypes to nva3.h

..., 0x03400640); @@ -375,15 +364,8 @@ nvaa_clock_prog(struct nouveau_clock *clk) } nv_wr32(clk, 0xc054, mast); - ret = 0; resume: - if (pfifo) - pfifo->start(pfifo, &flags); - - nv_mask(clk, 0x002504, 0x00000001, 0x00000000); - nv_wr32(clk, 0x020060, ptherm_gate); - /* Disable some PLLs and dividers when unused */ if (priv->csrc != nv_clk_src_core) { nv_wr32(clk, 0x4040, 0x00000000); @@ -395,6 +377,12 @@ resume: nv_mask(clk, 0x4020, 0x80000000, 0x00000000); } +out: + if (ret == -EBUSY) + f = NULL; + + nva3_clock_post(clk, f); + return ret; } -- 1.9.3

...ower than + * desired rather than higher */ + if (diff < 0) { + sdiv++; + oclk = (sclk * 2) / sdiv; + } + + /* divider can go as low as 2, limited here because NVIDIA * and the VBIOS on my NVA8 seem to prefer using the PLL * for 810MHz - is there a good reason? - */ + * XXX: PLLs with refclk 810MHz? */ if (sdiv > 4) { - oclk = (sclk * 2) / sdiv; - diff = khz - oclk; - if (!pll || (diff >= -2000 && diff < 3000)) { - info->clk = (((sdiv - 2) << 16) | 0x00003100); - return oclk; - } + info->clk = (((sdiv - 2) << 16) | 0x00...