search for: pll

...a3.c index a08011c..b9ab90a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c @@ -163,17 +163,12 @@ nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) } int -nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, +nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz, struct nva3_clock_info *info) { - struct nouveau_bios *bios = nouveau_bios(clock); struct nva3_clock_priv *priv = (void *)clock; - struct nvbios_pll limits; - u32 oclk, sclk, sdiv; - int P, N, M, diff; - int ret; + u32 oc...

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which con...

Following a series of patches to improve nouveaus clock tree parsing. Reclocking these engines (all but memory) is pretty stable on the cards I've tested. Please review and merge when approved. These patches do not solve the problem that core/shader engine doesn't like to be clocked up too far without fb following, with visible corruption as a result. I suspect this problem is unrelated

...everything is set up right, sorry for the noise here, but I don't want to try with an empty mail :) as the subject already says, this patch fixes one of the more serious issues while reclocking gddr5 on kepler cards. It works for me and for a bunch of others I met on IRC. Karol Herbst (1): pll/gk104: fix PLL instability due to bad configuration with gddr5 drm/nouveau/nvkm/subdev/clk/Kbuild | 1 + drm/nouveau/nvkm/subdev/clk/pll.h | 5 +++ drm/nouveau/nvkm/subdev/clk/pllgk104.c | 77 ++++++++++++++++++++++++++++++++++ drm/nouveau/nvkm/subdev/clk/pllgt215.c | 6 +++ drm/nouve...

...+ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -366,11 +366,20 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) if (info->coef) { nvkm_wr32(device, addr + 0x04, info->coef); nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); - nvkm_msec(device, 2000, + + /* Test PLL lock */ + nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); + if (nvkm_msec(device, 2000, if (nvkm_rd32(device, addr + 0x00) & 0x00020000) break; - ); - nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); + ) < 0) { + nvkm_warn(&clk->base.subdev, +...

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but seemed it wasn't used nowhere for CLK settings. Removing this works fine, but I don't know what it's really for. Actual bit setting this BYPASS_PLL_CHECK is on 0x10:...

Fixes regression introduced in commit 70790f4f "drm/nouveau/clock: pull in the implementation from all over the place" When code was moved from nv50_crtc_set_clock to nvc0_clock_pll_set, the PLLs it is used for got limited to only the first two VPLLs. nv50_crtc_set_clock was only called to change VPLLs, so it didn't limit what it was used for in any way. Since nvc0_clock_pll_set is used for all PLLs, it has to specify which PLLs the code is used for, and only listed the f...

Hello Ben Skeggs, The patch 88524bc06926: "drm/nouveau/devinit: move simple pll setting routines to devinit" from Mar 5, 2013, leads to the following static checker warning: drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c:53 nv50_devinit_pll_set() info: return a literal instead of 'ret' drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c 34 int 35...

...t speedo of Tegra X1. Ben, it would be super-duper great if you could take these in for 4.6. Not too big a deal if you cannot however. Alexandre Courbot (15): volt/gk20a: split constructor volt: add GM20B driver clk/gk20a: convert parameters to Khz clk/gk20a: reorganize variables in gk20a_pllg_calc_mnp() clk/gk20a: rename enable/disable functions clk/gk20a: fix VCO bit mask clk/gk20a: only compute n_lo if needed clk/gk20a: only restore divider to 1:1 if needed clk/gk20a: emit parent rate as debug message clk/gk20a: put mnp values into their own struct clk/gk20a: abstract p...

...u/nvkm/subdev/clk/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -366,11 +366,17 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) if (info->coef) { nvkm_wr32(device, addr + 0x04, info->coef); nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); + + /* Test PLL lock */ + nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000); nvkm_msec(device, 2000, if (nvkm_rd32(device, addr + 0x00) & 0x00020000) break; ); - nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); + nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010); + +...

From: Tom Rix <trix at redhat.com> clang static analysis flags this problem hw.c:271:12: warning: The left operand of '>=' is a garbage value if (pv.M1 >= pll_lim.vco1.min_m ... ~~~~~ ^ This is mostly not a problem because an early check in nouveau_hw_fix_bad_vpll() if (nvbios_pll_parse(bios, pll, &pll_lim)) return; nouveau_hw_get_pllvals(dev, pll, &pv); shadows a similar check in nouveau_hw_get_pllvals() ret = nvbios_pll_par...

...17 +++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 2 ++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c | 1 + 10 files changed, 28 insertions(+) diff --git a...

...ct echo cancelltion effect in the same computers? What should we do to use AEC in most computers? (Don't tell me to change a sound card.) >> >> From: Steve Underwood <steveu at coppice.org <mailto:steveu at coppice.org>> >> >> > It seems some cards use a PLL for their ADC, so they can lock to an >> > incoming SPDIF signal, but always use a local crystal clock source for >> > their DAC. These cards do not have their ADC and DAC synchronised. >> >> Do common on-board or PCI sound card lock to some incoming signal? >> &...

From: Steve Underwood <steveu at coppice.org> > It seems some cards use a PLL for their ADC, so they can lock to an > incoming SPDIF signal, but always use a local crystal clock source for > their DAC. These cards do not have their ADC and DAC synchronised. Do common on-board or PCI sound card lock to some incoming signal? Yes, there is a crystal oscillator and a PLL o...

...amp; git repos Chris Ball (2): Build fix for EXA 3 Revert "Build fix for EXA 3" Stefan Dirsch (1): Prevent MergedFB setups from crashing. Thomas Jaeger (1): Fall back to software for unsupported repeat modes Yannick Heneault (9): fixed winbond/nuvoton min pll clock to correct value (18.75Mhz). Fixed PLL m,n,p selection for G200eW to respect byte granularity. Updated PLL algorithm for G200eW. Fixed bad access issues and ddc1 implementation for IP core. Modified memory count rountine for G200eW to detect up to 16Megs. fixed m...

...eau-y += core/subdev/clock/nv40.o nouveau-y += core/subdev/clock/nv50.o nouveau-y += core/subdev/clock/nv84.o nouveau-y += core/subdev/clock/nva3.o +nouveau-y += core/subdev/clock/nvaa.o nouveau-y += core/subdev/clock/nvc0.o nouveau-y += core/subdev/clock/nve0.o nouveau-y += core/subdev/clock/pllnv04.o diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c index db13982..db3fc7b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c @@ -283,7 +283,7 @@ nv50_identify(st...

...eau-y += core/subdev/clock/nv40.o nouveau-y += core/subdev/clock/nv50.o nouveau-y += core/subdev/clock/nv84.o nouveau-y += core/subdev/clock/nva3.o +nouveau-y += core/subdev/clock/nvaa.o nouveau-y += core/subdev/clock/nvc0.o nouveau-y += core/subdev/clock/nve0.o nouveau-y += core/subdev/clock/pllnv04.o diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c index db13982..db3fc7b 100644 --- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c @@ -283,7 +283,7 @@ nv50_identify(st...

From: Tom Rix <trix at redhat.com> A break is not needed if it is preceded by a return or break Signed-off-by: Tom Rix <trix at redhat.com> --- drivers/gpu/drm/mgag200/mgag200_mode.c | 5 ----- drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c | 3 --- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c | 1 - drivers/gpu/drm/qxl/qxl_ioctl.c | 1 - 6 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm...

http://bugs.freedesktop.org/show_bug.cgi?id=24668 Summary: KMS does not work with nva8 Product: xorg Version: unspecified Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists.freedesktop.org ReportedBy:

I have looked at problem with Fermi GPUs where changing to higher clock led to really bad perfomance (with GpuTest 20x worse perfomance) and later also crashes of the nouveau. It seemed to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have tried to search this BYPASS_PLL_CHECK in Nvidia traces but seemed it wasn't used nowhere for CLK settings. Removing this works fine, but I don't know what it's really for. Actual bit setting this BYPASS_PLL_CHECK is on 0x10:...