search for: pci_write_config_dword

..._MASK) == - PCI_BASE_ADDRESS_MEM_TYPE_64) - goto found; - - return; -found: - start = pci_resource_start(dev, i); - size = pci_resource_len(dev, i); + start = pci_resource_start(dev, 1); + size = pci_resource_len(dev, 1); if (!start || size != 0x400000 || start & (size - 1)) return; - pci_write_config_dword(dev, 0x10 + i * 4, 0); - pci_resource_start(dev, i) = 0; - pci_resource_end(dev, i) = size - 1; - pci_write_config_dword(dev, 0x184, start); - pci_write_config_dword(dev, 0x190, start + size / 2); + pci_resource_flags(dev, 1) = 0; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); + pci_write_co...

...common + offsetof(struct virtio_pci_cap, > + offset), > + &offset); > + > + /* Program cfg capability for dword access into common cfg. */ > + pci_write_config_byte(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.bar), > + bar); > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.length), > + 0x4); > + > + /* Select features dword that has VIRTIO_F_IOMMU_PLATFORM. */ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset...

...common + offsetof(struct virtio_pci_cap, > + offset), > + &offset); > + > + /* Program cfg capability for dword access into common cfg. */ > + pci_write_config_byte(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.bar), > + bar); > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.length), > + 0x4); > + > + /* Select features dword that has VIRTIO_F_IOMMU_PLATFORM. */ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset...

...O Base/Limit */ + pcibios_resource_to_bus(dev, &region, res); + if (res->flags & IORESOURCE_MEM && + !(res->flags & IORESOURCE_PREFETCH)) { + l = (region.start >> 16) & 0xfff0; + l |= region.end & 0xfff00000; + } else { + l = 0x0000fff0; + } + pci_write_config_dword(dev, PCI_MEMORY_BASE, l); + + break; + + case 9 : /* Prefetchable MMIO Base/Limit */ + /* Clear out the upper 32 bits of PREF limit. + * If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily + * disables PREF range, which is ok. + */ + pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32,...

...common + offsetof(struct virtio_pci_cap, > + offset), > + &offset); > + > + /* Program cfg capability for dword access into common cfg. */ > + pci_write_config_byte(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.bar), > + bar); > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.length), > + 0x4); > + > + /* Select features dword that has VIRTIO_F_IOMMU_PLATFORM. */ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset...

...common + offsetof(struct virtio_pci_cap, > + offset), > + &offset); > + > + /* Program cfg capability for dword access into common cfg. */ > + pci_write_config_byte(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.bar), > + bar); > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.length), > + 0x4); > + > + /* Select features dword that has VIRTIO_F_IOMMU_PLATFORM. */ > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > + cap.offset), > + offset...

...; > > + &offset); > > > + > > > + /* Program cfg capability for dword access into common cfg. */ > > > + pci_write_config_byte(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > + cap.bar), > > > + bar); > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > + cap.length), > > > + 0x4); > > > + > > > + /* Select features dword that has VIRTIO_F_IOMMU_PLATFORM. */ > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap,...

...; > > + &offset); > > > + > > > + /* Program cfg capability for dword access into common cfg. */ > > > + pci_write_config_byte(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > + cap.bar), > > > + bar); > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > + cap.length), > > > + 0x4); > > > + > > > + /* Select features dword that has VIRTIO_F_IOMMU_PLATFORM. */ > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap,...

...&bar); + pci_read_config_dword(dev, common + offsetof(struct virtio_pci_cap, + offset), + &offset); + + /* Program cfg capability for dword access into common cfg. */ + pci_write_config_byte(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + cap.bar), + bar); + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + cap.length), + 0x4); + + /* Select features dword that has VIRTIO_F_IOMMU_PLATFORM. */ + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + cap.offset), + offset + offsetof(struct virtio_pci_commo...

...&bar); + pci_read_config_dword(dev, common + offsetof(struct virtio_pci_cap, + offset), + &offset); + + /* Program cfg capability for dword access into common cfg. */ + pci_write_config_byte(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + cap.bar), + bar); + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + cap.length), + 0x4); + + /* Select features dword that has VIRTIO_F_IOMMU_PLATFORM. */ + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, + cap.offset), + offset + offsetof(struct virtio_pci_commo...

Legacy virtio devices always bypassed an IOMMU, so using them with vfio was never safe. This adds a quirk detecting these and disabling VFIO unless the noiommu mode is used. At the moment, this only applies to virtio-pci devices. The patch might make sense on stable as well. Michael S. Tsirkin (2): vfio: report group noiommu status vfio: add virtio pci quirk

Legacy virtio devices always bypassed an IOMMU, so using them with vfio was never safe. This adds a quirk detecting these and disabling VFIO unless the noiommu mode is used. At the moment, this only applies to virtio-pci devices. The patch might make sense on stable as well. Michael S. Tsirkin (2): vfio: report group noiommu status vfio: add virtio pci quirk

...RESS_0 + 4 * resno; - } else if (resno == PCI_ROM_RESOURCE) { - if (!(res->flags & IORESOURCE_ROM_ENABLE)) - return; - new |= PCI_ROM_ADDRESS_ENABLE; - reg = dev->rom_base_reg; - } else { - /* Hmm, non-standard resource. */ - - return; /* kill uninitialised var warning */ - } - - pci_write_config_dword(dev, reg, new); - pci_read_config_dword(dev, reg, &check); + pci_write_config_dword(dev, pos, new); + pci_read_config_dword(dev, pos, &check); if ((new ^ check) & mask) { - dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", - resno, new, check); + d...

...RESS_0 + 4 * resno; - } else if (resno == PCI_ROM_RESOURCE) { - if (!(res->flags & IORESOURCE_ROM_ENABLE)) - return; - new |= PCI_ROM_ADDRESS_ENABLE; - reg = dev->rom_base_reg; - } else { - /* Hmm, non-standard resource. */ - - return; /* kill uninitialised var warning */ - } - - pci_write_config_dword(dev, reg, new); - pci_read_config_dword(dev, reg, &check); + pci_write_config_dword(dev, pos, new); + pci_read_config_dword(dev, pos, &check); if ((new ^ check) & mask) { - dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", - resno, new, check); + d...

...RESS_0 + 4 * resno; - } else if (resno == PCI_ROM_RESOURCE) { - if (!(res->flags & IORESOURCE_ROM_ENABLE)) - return; - new |= PCI_ROM_ADDRESS_ENABLE; - reg = dev->rom_base_reg; - } else { - /* Hmm, non-standard resource. */ - - return; /* kill uninitialised var warning */ - } - - pci_write_config_dword(dev, reg, new); - pci_read_config_dword(dev, reg, &check); + pci_write_config_dword(dev, pos, new); + pci_read_config_dword(dev, pos, &check); if ((new ^ check) & mask) { - dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n", - resno, new, check); + d...

..., > > + offset), > > + &offset); > > + > > + /* Program cfg capability for dword access into common cfg. */ > > + pci_write_config_byte(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > + cap.bar), > > + bar); > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > + cap.length), > > + 0x4); > > + > > + /* Select features dword that has VIRTIO_F_IOMMU_PLATFORM. */ > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > + cap.o...

.....b10c77bbe4716 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5549,7 +5549,7 @@ static void quirk_nvidia_hda(struct pci_dev *gpu) if (val & BIT(25)) return; - pci_info(gpu, "Enabling HDA controller\n"); + pci_dbg(gpu, "Enabling HDA controller\n"); pci_write_config_dword(gpu, 0x488, val | BIT(25)); /* The GPU becomes a multi-function device when the HDA is enabled */ -- 2.39.2

This is an attempt to allow enabling IOMMU for DMA. Design: - new feature bit IOMMU_PLATFORM which means host won't bypass IOMMU - virtio core uses DMA API if it sees IOMMU_PLATFORM - add quirk for vfio to disable device unless IOMMU_PLATFORM is set or the no-iommu mode is enabled - while I'm not sure how it will be used, it seems like a good idea to also have

This is an attempt to allow enabling IOMMU for DMA. Design: - new feature bit IOMMU_PLATFORM which means host won't bypass IOMMU - virtio core uses DMA API if it sees IOMMU_PLATFORM - add quirk for vfio to disable device unless IOMMU_PLATFORM is set or the no-iommu mode is enabled - while I'm not sure how it will be used, it seems like a good idea to also have

...et); > > > > + > > > > + /* Program cfg capability for dword access into common cfg. */ > > > > + pci_write_config_byte(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > > + cap.bar), > > > > + bar); > > > > + pci_write_config_dword(dev, cfg + offsetof(struct virtio_pci_cfg_cap, > > > > + cap.length), > > > > + 0x4); > > > > + > > > > + /* Select features dword that has VIRTIO_F_IOMMU_PLATFORM. */ > > > > + pci_write_config_dword(dev, cfg + offsetof(s...