Yu Zhao
2009-Apr-03 08:04 UTC
[Xen-devel] [PATCH] PCI: sync up the SR-IOV changes between Dom0 and upstream kernels
The SR-IOV patches for the upstream kernel are finally in-tree. This
patch backports some minor changes that appeared in the upstream kernel
after the Dom0 patches were checked-in.
Signed-off-by: Yu Zhao <yu.zhao@intel.com>
diff -r 67a7ffcc5067 -r 0e265f73b23a drivers/pci/Kconfig
--- a/drivers/pci/Kconfig Wed Apr 01 11:43:01 2009 +0100
+++ b/drivers/pci/Kconfig Fri Apr 03 03:48:47 2009 -0400
@@ -41,8 +41,8 @@
bool "PCI IOV support"
depends on PCI
help
- PCI-SIG I/O Virtualization (IOV) Specifications support.
- Single Root IOV: allows the creation of virtual PCI devices
- that share the physical resources from a real device.
+ I/O Virtualization is a PCI feature supported by some devices
+ which allows them to create virtual devices which share their
+ physical resources.
- When in doubt, say N.
+ If unsure, say N.
diff -r 67a7ffcc5067 -r 0e265f73b23a drivers/pci/iov.c
--- a/drivers/pci/iov.c Wed Apr 01 11:43:01 2009 +0100
+++ b/drivers/pci/iov.c Fri Apr 03 03:48:47 2009 -0400
@@ -309,16 +309,16 @@
if (!total)
return 0;
+ ctrl = 0;
list_for_each_entry(pdev, &dev->bus->devices, bus_list)
if (pdev->is_physfn)
- break;
- if (list_empty(&dev->bus->devices) || !pdev->is_physfn)
- pdev = NULL;
+ goto found;
- ctrl = 0;
- if (!pdev && pci_ari_enabled(dev->bus))
+ pdev = NULL;
+ if (pci_ari_enabled(dev->bus))
ctrl |= PCI_SRIOV_CTRL_ARI;
+found:
pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, ctrl);
pci_write_config_word(dev, pos + PCI_SRIOV_NUM_VF, total);
pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
@@ -507,6 +507,7 @@
/**
* pci_enable_sriov - enable the SR-IOV capability
* @dev: the PCI device
+ * @nr_virtfn: number of Virtual Functions to enable
*
* Returns 0 on success, or negative on failure.
*/
diff -r 67a7ffcc5067 -r 0e265f73b23a drivers/pci/quirks.c
--- a/drivers/pci/quirks.c Wed Apr 01 11:43:01 2009 +0100
+++ b/drivers/pci/quirks.c Fri Apr 03 03:48:47 2009 -0400
@@ -1749,58 +1749,49 @@
#endif
#ifdef CONFIG_PCI_IOV
+
/*
- * If BIOS doesn''t allocate resources for SR-IOV BARs, zero Flash BAR
- * and program SR-IOV BARs to use the old Flash Memory Space.
- * PCI subsystem may try to allocate Memory Space for Flash BAR later,
- * that''s why we don''t clear Flash BAR flags.
+ * For Intel 82576 SR-IOV NIC, if BIOS doesn''t allocate resources for
the
+ * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the
+ * old Flash Memory Space.
*/
-static void __devinit intel_82576_quirk(struct pci_dev *dev)
+static void __devinit quirk_i82576_sriov(struct pci_dev *dev)
{
- int i, flags;
+ int pos, flags;
u32 bar, start, size;
if (PAGE_SIZE > 0x10000)
return;
- if (pci_read_config_dword(dev, 0x184, &bar))
+ flags = pci_resource_flags(dev, 0);
+ if ((flags & PCI_BASE_ADDRESS_SPACE) !+ PCI_BASE_ADDRESS_SPACE_MEMORY ||
+ (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) !+
PCI_BASE_ADDRESS_MEM_TYPE_32)
return;
+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
+ if (!pos)
+ return;
+
+ pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar);
if (bar & PCI_BASE_ADDRESS_MEM_MASK)
return;
- i = 1;
- flags = pci_resource_flags(dev, i);
- if ((flags & PCI_BASE_ADDRESS_SPACE) =- PCI_BASE_ADDRESS_SPACE_MEMORY
&&
- (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) =-
PCI_BASE_ADDRESS_MEM_TYPE_32)
- goto found;
-
- i = 2;
- flags = pci_resource_flags(dev, i);
- if ((flags & PCI_BASE_ADDRESS_SPACE) =- PCI_BASE_ADDRESS_SPACE_MEMORY
&&
- (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) =-
PCI_BASE_ADDRESS_MEM_TYPE_64)
- goto found;
-
- return;
-found:
- start = pci_resource_start(dev, i);
- size = pci_resource_len(dev, i);
+ start = pci_resource_start(dev, 1);
+ size = pci_resource_len(dev, 1);
if (!start || size != 0x400000 || start & (size - 1))
return;
- pci_write_config_dword(dev, 0x10 + i * 4, 0);
- pci_resource_start(dev, i) = 0;
- pci_resource_end(dev, i) = size - 1;
- pci_write_config_dword(dev, 0x184, start);
- pci_write_config_dword(dev, 0x190, start + size / 2);
+ pci_resource_flags(dev, 1) = 0;
+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
+ pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start);
+ pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2);
dev_info(&dev->dev, "use Flash Memory Space for SR-IOV
BARs\n");
}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, intel_82576_quirk);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, intel_82576_quirk);
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, intel_82576_quirk);
-#endif /* CONFIG_PCI_IOV */
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov);
+
+#endif /* CONFIG_PCI_IOV */
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