search for: pci_read_bases

...num pci_bar_type type, +int pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int pos) { u32 l, sz, mask; @@ -299,6 +299,7 @@ static int __pci_read_base(struct pci_de res->flags = 0; goto out; } +EXPORT_SYMBOL_GPL(pci_read_base); static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) { @@ -307,7 +308,7 @@ static void pci_read_bases(struct pci_de for (pos = 0; pos < howmany; pos++) { struct resource *res = &dev->resource[pos]; reg = PCI_BASE_ADDRESS_0 + (pos << 2); - pos += __pci_read_base(dev, pci_bar...

...num pci_bar_type type, +int pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int pos) { u32 l, sz, mask; @@ -299,6 +299,7 @@ static int __pci_read_base(struct pci_de res->flags = 0; goto out; } +EXPORT_SYMBOL_GPL(pci_read_base); static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) { @@ -307,7 +308,7 @@ static void pci_read_bases(struct pci_de for (pos = 0; pos < howmany; pos++) { struct resource *res = &dev->resource[pos]; reg = PCI_BASE_ADDRESS_0 + (pos << 2); - pos += __pci_read_base(dev, pci_bar...

...num pci_bar_type type, +int pci_read_base(struct pci_dev *dev, enum pci_bar_type type, struct resource *res, unsigned int pos) { u32 l, sz, mask; @@ -299,6 +299,7 @@ static int __pci_read_base(struct pci_de res->flags = 0; goto out; } +EXPORT_SYMBOL_GPL(pci_read_base); static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) { @@ -307,7 +308,7 @@ static void pci_read_bases(struct pci_de for (pos = 0; pos < howmany; pos++) { struct resource *res = &dev->resource[pos]; reg = PCI_BASE_ADDRESS_0 + (pos << 2); - pos += __pci_read_base(dev, pci_bar...

...ASE_ADDRESS_MEM_MASK; } - } else { - res->flags |= (l & IORESOURCE_ROM_ENABLE); - l &= PCI_ROM_ADDRESS_MASK; - mask = (u32)PCI_ROM_ADDRESS_MASK; } if (type == pci_bar_mem64) { @@ -335,7 +331,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) for (pos = 0; pos < howmany; pos++) { struct resource *res = &dev->resource[pos]; reg = PCI_BASE_ADDRESS_0 + (pos << 2); - pos += __pci_read_base(dev, pci_bar_unknown, res, reg)...

...ASE_ADDRESS_MEM_MASK; } - } else { - res->flags |= (l & IORESOURCE_ROM_ENABLE); - l &= PCI_ROM_ADDRESS_MASK; - mask = (u32)PCI_ROM_ADDRESS_MASK; } if (type == pci_bar_mem64) { @@ -335,7 +331,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) for (pos = 0; pos < howmany; pos++) { struct resource *res = &dev->resource[pos]; reg = PCI_BASE_ADDRESS_0 + (pos << 2); - pos += __pci_read_base(dev, pci_bar_unknown, res, reg)...

...= decode_bar(res, l); res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; if (type == pci_bar_io) { @@ -321,6 +319,7 @@ static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags = 0; goto out; } +EXPORT_SYMBOL_GPL(pci_read_base); static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) { @@ -329,7 +328,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) for (pos = 0; pos < howmany; pos++) { struct resource *res = &dev->resource[pos]; reg = PCI_BASE_ADDRESS_0 + (pos << 2);...

...= decode_bar(res, l); res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; if (type == pci_bar_io) { @@ -321,6 +319,7 @@ static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags = 0; goto out; } +EXPORT_SYMBOL_GPL(pci_read_base); static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) { @@ -329,7 +328,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) for (pos = 0; pos < howmany; pos++) { struct resource *res = &dev->resource[pos]; reg = PCI_BASE_ADDRESS_0 + (pos << 2);...

...= decode_bar(res, l); res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; if (type == pci_bar_io) { @@ -321,6 +319,7 @@ static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, res->flags = 0; goto out; } +EXPORT_SYMBOL_GPL(pci_read_base); static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) { @@ -329,7 +328,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) for (pos = 0; pos < howmany; pos++) { struct resource *res = &dev->resource[pos]; reg = PCI_BASE_ADDRESS_0 + (pos << 2);...

Greetings, Patches to support Single Root I/O Virtualization (SR-IOV) capability are available for the Linux 2.6 development tree. KVM and Xen supports will come soon! --- Single Root I/O Virtualization (SR-IOV) capability defined by PCI-SIG is intended to enable multiple system software to share PCI hardware resources. PCI device that supports this capability can be extended to one Physical

Add Single Root I/O Virtualization (SR-IOV) support. Cc: Jesse Barnes <jbarnes at virtuousgeek.org> Cc: Randy Dunlap <randy.dunlap at oracle.com> Cc: Grant Grundler <grundler at parisc-linux.org> Cc: Alex Chiang <achiang at hp.com> Cc: Matthew Wilcox <matthew at wil.cx> Cc: Roland Dreier <rdreier at cisco.com> Cc: Greg KH <greg at kroah.com>

Add Single Root I/O Virtualization (SR-IOV) support. Cc: Jesse Barnes <jbarnes at virtuousgeek.org> Cc: Randy Dunlap <randy.dunlap at oracle.com> Cc: Grant Grundler <grundler at parisc-linux.org> Cc: Alex Chiang <achiang at hp.com> Cc: Matthew Wilcox <matthew at wil.cx> Cc: Roland Dreier <rdreier at cisco.com> Cc: Greg KH <greg at kroah.com>

Centralize capability related functions into several new functions and put PCI resource definitions into an enum. Cc: Jesse Barnes <jbarnes at virtuousgeek.org> Cc: Randy Dunlap <randy.dunlap at oracle.com> Cc: Grant Grundler <grundler at parisc-linux.org> Cc: Alex Chiang <achiang at hp.com> Cc: Matthew Wilcox <matthew at wil.cx> Cc: Roland Dreier <rdreier at

Centralize capability related functions into several new functions and put PCI resource definitions into an enum. Cc: Jesse Barnes <jbarnes at virtuousgeek.org> Cc: Randy Dunlap <randy.dunlap at oracle.com> Cc: Grant Grundler <grundler at parisc-linux.org> Cc: Alex Chiang <achiang at hp.com> Cc: Matthew Wilcox <matthew at wil.cx> Cc: Roland Dreier <rdreier at

[PATCH 3/4] PCI: support SR-IOV capability Support SR-IOV capability. By default, this feature is not enabled and the Physical Function behaves as normal PCIe device. After it's enabled, each Virtual Function's PCI configuration space can be accessed using its own Bus, Device and Function Number (Routing ID). Each Virtual Function also has PCI Memory Space, which is used to map its own

[PATCH 3/4] PCI: support SR-IOV capability Support SR-IOV capability. By default, this feature is not enabled and the Physical Function behaves as normal PCIe device. After it's enabled, each Virtual Function's PCI configuration space can be accessed using its own Bus, Device and Function Number (Routing ID). Each Virtual Function also has PCI Memory Space, which is used to map its own

[PATCH 3/4] PCI: support SR-IOV capability Support SR-IOV capability. By default, this feature is not enabled and the Physical Function behaves as normal PCIe device. After it's enabled, each Virtual Function's PCI configuration space can be accessed using its own Bus, Device and Function Number (Routing ID). Each Virtual Function also has PCI Memory Space, which is used to map its own

...be(struct pci_dev *dev, +static int pcie_portdrv_probe(struct pci_dev *dev, const struct pci_device_id *id) { int status; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 3d17641..edc3d12 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -305,7 +305,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) } } -static void __devinit pci_read_bridge_io(struct pci_bus *child) +static void pci_read_bridge_io(struct pci_bus *child) { struct pci_dev *dev = child->self; u8 io_base_lo, io_limit_lo; @@ -345,7 +345,7 @@ static void __devinit pci...

...be(struct pci_dev *dev, +static int pcie_portdrv_probe(struct pci_dev *dev, const struct pci_device_id *id) { int status; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 3d17641..edc3d12 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -305,7 +305,7 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) } } -static void __devinit pci_read_bridge_io(struct pci_bus *child) +static void pci_read_bridge_io(struct pci_bus *child) { struct pci_dev *dev = child->self; u8 io_base_lo, io_limit_lo; @@ -345,7 +345,7 @@ static void __devinit pci...

Add Single Root I/O Virtualization (SR-IOV) support. Signed-off-by: Yu Zhao <yu.zhao@intel.com> diff -r 040046b91eb7 -r 75504b97c0ab drivers/pci/Kconfig --- a/drivers/pci/Kconfig Sat Sep 27 01:25:31 2008 -0400 +++ b/drivers/pci/Kconfig Sat Sep 27 01:27:01 2008 -0400 @@ -27,3 +27,14 @@ When in doubt, say N. +config PCI_IOV + bool "PCI SR-IOV support"

Support SR-IOV capability. By default, this feature is not enabled and the SR-IOV device behaves as traditional PCI device. After it's enabled, each Virtual Function's PCI configuration space can be accessed using its own Bus, Device and Function Number (Routing ID). Each Virtual Function also has PCI Memory Space, which is used to map its own register set. Signed-off-by: Yu Zhao